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ADC12QJ1600ALREP Scheda tecnica(PDF) 70 Page - Texas Instruments |
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ADC12QJ1600ALREP Scheda tecnica(HTML) 70 Page - Texas Instruments |
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70 / 148 page  Table 8-14. JESD204C Initial Lane Alignment Sequence Parameters PARAMETER DESCRIPTION USER CONFIGURED OR DERIVED VALUE ADJCNT LMFC adjustment amount (not applicable) Derived Always 0 ADJDIR LMFC adjustment direction (not applicable) Derived Always 0 BID Bank ID Derived Always 0 CF Number of control words per frame Derived Always 0 CS Control bits per sample Derived Always set to 0 in ILAS, see Table 8-15 for actual usage DID Device identifier, used to identify the link User configured Set by DID, see Table 8-16 F Number of octets (bytes) per frame (per lane) Derived See Table 8-15 HD High-density format (samples split between lanes) Derived Always 0 JESDV JESD204 standard revision Derived Always 1 K Number of frames per multiframe User configured Set by the KM1 register L Number of serial output lanes per link Derived See Table 8-15 LID Lane identifier for each lane Derived See Table 8-16 M Number of converters used to determine lane bit packing; may not match number of ADC channels in the device Derived See Table 8-15 N Sample resolution (before adding control and tail bits) Derived See Table 8-15 N' Bits per sample after adding control and tail bits Derived See Table 8-15 S Number of samples per converter (M) per frame Derived See Table 8-15 SCR Scrambler enabled User configured Set by SCR SUBCLASSV Device subclass version Derived Always 1 RES1 Reserved field 1 Derived Always 0 RES2 Reserved field 2 Derived Always 0 CHKSUM Checksum for ILAS checking (sum of all above parameters modulo 256) Derived Computed based on parameters in this table ADC12QJ1600-EP SBASAJ4A – JUNE 2022 – REVISED DECEMBER 2022 www.ti.com 70 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADC12QJ1600-EP |
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