ADC12QJ1600ALREP datasheet(21/148 Pages) TI

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7.8 Timing Requirements

MIN

NOM

MAX

UNIT

ADC SAMPLING CLOCK

ADC core sampling clock frequency

High Performance Mode

500(1)

1600(1)

MHz

Low Power Mode

1000(1)

ADC core minimum sampling clock frequency

Low Power Mode

500(1)

ADC core sampling clock period

High Performance Mode

625(1)

2000(1)

Low Power Mode

1000(1)

ADC core maximum sampling clock period

Low Power Mode

2000(1)

CLOCK INPUTS (CLK+, CLK–, SE_CLK)

fCLK

CLK± input frequency

PLL Disabled

500

1600

MHz

PLL Enabled, PLLREF_SE

= 0

500

fSE_CLK

SE_CLK input frequency

PLL Enabled, PLLREF_SE

= 1

500

MHz

DC(CLKMIN)

Minimum Input clock duty cycle (CLK± and SE_CLK)

Input clock duty cycle

(CLK± and SE_CLK)

40%

DC(CLKMAX)

Maximum Input clock duty cycle (CLK± and SE_CLK)

60%

PHASE-LOCKED LOOP (PLL) AND VOLTAGE-CONTROLLED OSCILLATOR (VCO)

fPLLPFD

PLL phase-frequency detector (PFD) frequency

PLL Enabled

500

MHz

fVCO

Closed-loop voltage-controlled oscillator (VCO) frequency PLL Enabled

7200

8200

MHz

SYSREF (SYSREF+, SYSREF–)

tINV(SYSREF)

Width of invalid SYSREF capture region of CLK± period, indicating setup or hold time

violation, as measured by SYSREF_POS status register(2)

250

tINV(TEMP)

Drift of invalid SYSREF capture region over temperature, positive number indicates a

shift toward MSB of SYSREF_POS register

0.05

ps/°C

tINV(VA11)

Drift of invalid SYSREF capture region over VA11 supply voltage, positive number

indicates a shift toward MSB of SYSREF_POS register

-0.17

ps/mV

tSTEP(SP)

Delay of SYSREF_POS LSB

SYSREF_ZOOM = 0

125

SYSREF_ZOOM = 1

DC(SYSREF)

SYSREF duty cycle (asserted) when using a periodic SYSREF signal

50%

55%

t(PH_SYS)

Minimum SYSREF± assertion duration after SYSREF± rising edge event

JESD204C SYNC TIMING (SYNCSE)

SERIAL PROGRAMMING INTERFACE (SCLK, SDI, SCS)

fCLK(SCLK)

Serial clock frequency

15.625

MHz

t(PH)

Serial clock high value pulse duration

t(PL)

Serial clock low value pulse duration

tSU(SCS)

Setup time from SCS to rising edge of SCLK

tH(SCS)

Hold time from rising edge of SCLK to SCS

tSU(SDI)

Setup time from SDI to rising edge of SCLK

tH(SDI)

Hold time from rising edge of SCLK to SDI

(1)

Unless functionally limited to a smaller range in the tables Operating Modes for Quad Channel Device based on programmed JMODE.

(2)

Use SYSREF_POS to select an optimal SYSREF_SEL value for the SYSREF capture, see the section SYSREF Windowing for

more information on SYSREF windowing. The invalid region, specified by tINV(SYSREF), indicates the portion of the CLK± period(tCLK),

as measured by SYSREF_SEL, that may result in a setup and hold violation. Verify that the timing skew between SYSREF± and

CLK± over system operating conditions from the nominal conditions (that used to find optimal SYSREF_SEL) does not result in the

invalid region occurring at the selected SYSREF_SEL position in SYSREF_POS, otherwise a temperature dependent SYSREF_SEL

selection may be needed to track the skew between CLK± and SYSREF±.

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ADC12QJ1600-EP

SBASAJ4A – JUNE 2022 – REVISED DECEMBER 2022

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