ADC12QJ1600ALREP datasheet(2/148 Pages) TI

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Table of Contents

1 Features............................................................................1

2 Applications..................................................................... 1

3 Description.......................................................................1

4 Description (continued).................................................. 2

5 Revision History.............................................................. 2

6 Pin Configuration and Functions...................................3

7 Specifications.................................................................. 8

7.1 Absolute Maximum Ratings........................................ 8

7.2 ESD Ratings............................................................... 8

7.3 Recommended Operating Conditions.........................9

Thermal Information..........................................................9

7.4 Electrical Characteristics: DC Specifications............ 10

7.5 Electrical Characteristics: Power Consumption........ 12

7.6 Electrical Characteristics: AC Specifications............ 14

7.7 Switching Characteristics..........................................19

7.8 Timing Requirements................................................21

7.9 Typical Characteristics.............................................. 22

8 Detailed Description......................................................46

8.1 Overview................................................................... 46

8.2 Functional Block Diagram......................................... 47

8.3 Feature Description...................................................48

8.4 Device Functional Modes..........................................68

8.5 Programming............................................................ 88

9 Application and Implementation................................ 128

9.1 Application Information........................................... 128

9.2 Typical Applications................................................ 128

9.3 Initialization Set Up................................................. 133

9.4 Power Supply Recommendations...........................134

9.5 Layout..................................................................... 136

10 Device and Documentation Support........................141

10.1 Device Support..................................................... 141

10.2 Receiving Notification of Documentation Updates141

10.3 Support Resources............................................... 141

10.4 Trademarks...........................................................141

10.5 Electrostatic Discharge Caution............................141

10.6 Glossary................................................................141

11 Mechanical, Packaging, and Orderable

Information.................................................................. 141

4 Description (continued)

A number of clocking features are included to relax system hardware requirements, such as an internal phase-

locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock

outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is

provided for pulsed systems.

JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB)

routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the

single channel device), with SerDes baud-rates up to 17.16 Gbps, to allow the optimal configuration for each

application.

5 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision * (June 2022) to Revision A (December 2022)

Page

• Changed the document from Advanced Information to Production data............................................................ 1

ADC12QJ1600-EP

SBASAJ4A – JUNE 2022 – REVISED DECEMBER 2022

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