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FT81X Embedded Video Engine Datasheet

Version 1.4

Document No.: BRT_000002 Clearance No.: BRT#004

1st Byte

2nd byte

3rd byte

Command

Description

Byte2 [1:0]

Pin Setting

Float

Pull-Down

Pull-Up

Reserved

Byte2[7:2] determine which pin/pin group

to set.

Please refer to the table in command

PINDRIVE entry.

Table 4-5 Host command list

NOTE: Any command code not specified is reserved and should not be used by the software

4.1.6

Interrupts

The interrupt output pin is enabled by REG_INT_EN. When REG_INT_EN is 0, INT_N is tri-state (pulled to

high by external pull-up resistor). When REG_INT_EN is 1, INT_N is driven low when any of the interrupt

flags in REG_INT_FLAGS are high, after masking with REG_INT_MASK. Writing a ‘1’ in any bit of

REG_INT_MASK will enable the corresponding interrupt. Each bit in REG_INT_FLAGS is set by a

corresponding interrupt source. REG_INT_FLAGS is readable by the host at any time, and clears when

read.

The INT_N pin is open-drain (OD) output by default. It can be configured to push-pull output by register

REG_GPIOX.

Bit

Interrupt Sources

CONVCOMPLETE

CMDFLAG

CMDEMPTY

PLAYBACK

Conditions

Touch-screen

conversions

completed

Command FIFO

flag

Command FIFO

empty

Audio playback

ended

Bit

Interrupt Sources

SOUND

TAG

TOUCH

SWAP

Conditions

Sound effect

ended

Touch-screen tag

value change

touch detected

Display list swap

occurred

Table 4-6 Interrupt Flags bit assignment

4.2 System Clock

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