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FT81X Embedded Video Engine Datasheet

Version 1.4

Document No.: BRT_000002 Clearance No.: BRT#004

Figure 4-3 Quad SPI Interface connection

4.1.2

Serial Data Protocol

The FT81x appears to the host MPU/MCU as a memory-mapped SPI device. The host communicates with

the FT81x using reads and writes to a large (4 megabyte) address space. Within this address space are

dedicated areas for graphics, audio and touch control. Refer to section 5 for the detailed memory map.

The host reads and writes the FT81x address space using SPI transactions. These transactions are

memory read, memory write and command write. Serial data is sent by the most significant bit first.

Each transaction starts with CS_N goes low, and ends when CS_N goes high. There’s no limit on data

length within one transaction, as long as the memory address is continuous.

4.1.3

Host Memory Read

For SPI memory read transactions, the host sends two zero bits, followed by the 22-bit address. This is

followed by a dummy byte. After the dummy byte, the FT81x responds to each host byte with read data

bytes.

Byte n

Table 4-2 Host memory read transaction

Address [21:16]

Address [15:8]

Address [7:0]

Dummy byte

Byte 0

GND

SCLK

MISO

IO2

SS#

PD#

INT#

SCK

IO1

IO2

CS_N

PD_N

INT_N

FT81x

1.8-3.3V

VCCIO1

3.3V

VCC

4.7k

MPU/MCU

MOSI

IO3

IO0

IO3

Read Data

Write

Address

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