FT813Q-R datasheet(27/63 Pages) BRIDGETEK

27 / 63 page

FT81X Embedded Video Engine Datasheet

Version 1.4

Document No.: BRT_000002 Clearance No.: BRT#004

PCLK frequency = System Clock frequency / REG_PCLK

The FT81x system clock frequency is programmable. Some of the possible PCLK frequencies that FT81x

supports are listed inError! Reference source not found..

REG_PCLK

System Clock Frequency (MHz)

60(default)

8.0

9.0

6.0

9.6

7.2

4.8

8.0

6.0

4.0

8.6

6.9

5.1

3.4

7.5

6.0

4.5

3.0

6.7

5.3

4.0

2.7

6.0

4.8

3.6

2.4

Table 4-11 RGB PCLK frequency

REG_PCLK_POL defines the clock polarity, with 0 for positive active clock edge, and 1 for negative clock

edge.

REG_CSPREAD controls the transition of RGB signals with respect to the PCLK active clock edge. When

REG_CSPREAD=0, R[7:0], G[7:0] and B[7:0] signals change following the active edge of PCLK. When

REG_CSPREAD=1, R[7:0] changes a PCLK clock early and B[7:0] a PCLK clock later, which helps reduce

the switching noise.

REG_DITHER enables colour dither. This option improves the half-tone appearance on displays.

Internally, the graphics engine computes the colour values at an 8 bit precision; however, the LCD colour

at a lower precision is sufficient. The FT810/FT811 output is only 6 bits per colour in 6:6:6 formats and a

2X2 dither matrix allow the truncated bits to contribute to the final colour values.

REG_OUTBITS gives the bit width of each colour channel, the default is 6/6/6(for FT810/FT811) or

8/8/8(for FT812/FT813) bits for each R/G/B colour. A lower value means fewer bits are output for each

channel allowing dithering on lower precision LCD displays.

REG_SWIZZLE controls the arrangement of the output colour pins, to help the PCB route different LCD

panel arrangements. Bit 0 of the register causes the order of bits in each colour channel to be reversed.

Bits 1-3 control the RGB order. Setting Bit 1 causes R and B channels to be swapped. Setting Bit 3 allows

rotation to be enabled. If Bit 3 is set, then (R,G,B) is rotated right if bit 2 is one, or left if bit 2 is zero.

REG_SWIZZLE

PINS (FT810/FT811, 6 bits)

PINS (FT812/FT813, 8 bits)

b3 b2 b1 b0 R7, R6, R5,

R4, R3, R2

G7, G6, G5,

G4, G3, G2

B7, B6, B5,

B4, B3, B2

R7, R6,

R5, R4,

R3, R2,

R1, R0

G7, G6,

G5, G4,

G3, G2,

G1, G0

B7, B6,

B5, B4,

B3, B2,

B1, B0

R[7:2]

G[7:2]

B[7:2]

R[7:0]

G[7:0]

B[7:0]

R[2:7]

G[2:7]

B[2:7]

R[0:7]

G[0:7]

B[0:7]

B[7:2]

G[7:2]

R[7:2]

B[7:0]

G[7:0]

R[7:0]

B[2:7]

G[2:7]

R[2:7]

B[0:7]

G[0:7]

R[0:7]

FT813Q-R Scheda tecnica(PDF) 27 Page - Bridgetek Pte Ltd.

FT813Q-R Scheda tecnica(HTML) 27 Page - Bridgetek Pte Ltd.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63

Scheda tecnica Scarica

Link URL