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FT81X Embedded Video Engine Datasheet

Version 1.4

Document No.: BRT_000002 Clearance No.: BRT#004

5 Memory Map

All memory and registers in the FT81x core are memory mapped in 22-bit address space with a 2-bit SPI

command prefix. Prefix 0'b00 for read and 0'b10 for write to the address space, 0'b01 is reserved for

Host Commands and 0'b11 undefined. The following are the memory space definition.

Start

Address

End

Address

Size

NAME

Description

00 0000h

0F FFFFh

1024 kB

RAM_G

General purpose graphics RAM

1E 0000h

2F FFFBh

1152 kB

ROM_FONT

Font table and bitmap

2F FFFCh

2F FFFFh

4 B

ROM_FONT_ADDR

Font table pointer address

30 0000h

30 1FFFh

8 kB

RAM_DL

Display List RAM

30 2000h

30 2FFFh

4 kB

RAM_REG

Registers

30 8000h

30 8FFFh

4 kB

RAM_CMD

Command buffer

Table 5-1 FT81x Memory Map

Note 1: The addresses beyond this table are reserved and shall not be read or written unless otherwise

specified.

5.1 Registers

The tableError! Reference source not found. shows the complete list of the FT81x registers. Refer to

FT81x_Series_Programmers_Guide, Chapter 2 for details of the register function.

Address

(hex)

Bit

Reset

value

Description

302000h

REG_ID

r/o

7Ch

Identification register, always reads as

7Ch

302004h

REG_FRAMES

r/o

Frame counter, since reset

302008h

REG_CLOCK

r/o

Clock cycles, since reset

30200Ch

REG_FREQUENCY

r/w

60000000

Main clock frequency (Hz)

302010h

REG_RENDERMODE

r/w

Rendering mode: 0 = normal, 1 = single-

line

302014h

REG_SNAPY

r/w

Scanline select for RENDERMODE 1

302018h

REG_SNAPSHOT

r/w

Trigger for RENDERMODE 1

30201Ch

REG_SNAPFORMAT

r/w

20h

Pixel format for scanline readout

302020h

REG_CPURESET

r/w

Graphics, audio and touch engines reset

control. Bit2: audio, bit1: touch, bit0:

graphics

302024h

REG_TAP_CRC

r/o

Live video tap crc. Frame CRC is

computed every DL SWAP.

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