FT812Q-R datasheet(18/63 Pages) BRIDGETEK

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FT81X Embedded Video Engine Datasheet

Version 1.4

Document No.: BRT_000002 Clearance No.: BRT#004

1st Byte

2nd byte

3rd byte

Command

Description

Byte2

[7:6]

sets the PLL range

When Byte2[5:0] = 0, 2, 3

When Byte2[5:0] = 4, 5

01101000b

00000000b

68h

RST_PULSE

Send reset pulse to FT81x core. The

behaviour is the same as POR except that

settings done through SPI commands will

not be affected

Configuration

01110000b

00000000b

70h

PINDRIVE

This will set the drive strength for various

pins. For FT800/FT801 compatibility, by

default those settings are from the GPIO

registers. FT81x supports setting the drive

strength via SPI command instead.

When PINDRIVE for a pin from the SPI

command is not updated, the drive strength

will be determined by its corresponding

GPIO register bits, if they exist. If they don’t

exist, a hard coded setting is used. Please

refer to Error! Reference source not

found. for default values.

When PINDRIVE for a pin from the SPI

command is updated, it will override the

corresponding setting in the GPIO register

bits.

Byte2 determines which pin and the setting

are to be updated.

Byte2[1:0] determine the drive strength:

Byte2

[1:0]

Drive Strength

5mA

10.0mA

15.0mA

20.0mA

Byte[7:2] determine which pin/pin group to

set:

Byte2

[7:2]

Pin / Pin Group

00h

GPIO 0

01h

GPIO 1

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