FT812Q-R datasheet(17/63 Pages) BRIDGETEK

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FT81X Embedded Video Engine Datasheet

Version 1.4

Document No.: BRT_000002 Clearance No.: BRT#004

1st Byte

2nd byte

3rd byte

Command

Description

01000001b

00000000b

41h

STANDBY

Put FT81x core to standby mode. Clock gate

off, PLL and Oscillator remain on (default).

ACTIVE command to wake up.

01000010b

00000000b

42h

SLEEP

Put FT81x core to sleep mode. Clock gate

off, PLL and Oscillator off. ACTIVE command

to wake up.

01000011b

01010000b

00000000b

43h/50h

PWRDOWN

Switch off 1.2V core voltage to the digital

core circuits. Clock, PLL and Oscillator off.

SPI is alive. ACTIVE command to wake up.

01000100b

00000000b

49h

PD_ROMS

Select power down individual ROMs; Byte2

determines which ROM to power down or

up. A 1 on a bit powers down the

corresponding block; a 0 on a bit powers up

the corresponding block. As these are not

readable, the host must remember the

setting on its own.

Byte2[7]

ROM_MAIN

Byte2[6]

ROM_RCOSATAN

Byte2[5]

ROM_SAMPLE

Byte2[4]

ROM_JABOOT

Byte2[3]

ROM_J1BOOT

Byte2[2-

reserved

Clock and Reset

01000100b

00000000b

44h

CLKEXT

Select PLL input from external crystal

oscillator or external input clock. No effect if

external clock is already selected, otherwise

a system reset will be generated

01001000b

00000000b

48h

CLKINT

Select PLL input from internal relaxation

oscillator (default). No effect if internal clock

is already selected, otherwise a system

reset will be generated

01100001b

01100010b

00000000b

61h/62h

CLKSEL

This command will only be effective when

the PLL is stopped (SLEEP mode).

For compatibility to FT800/FT801, set Byte2

to 0x00. This will set the PLL clock back to

default (60 MHz).

Byte2

[5:0]

sets the clock frequency

Set to default clock speed

Reserved

2 to 5

2 to 5 times the osc

frequency (i.e. 24 to 60MHz

with 12MHz oscillator)

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