FT812Q-R datasheet(36/63 Pages) BRIDGETEK

36 / 63 page

FT81X Embedded Video Engine Datasheet

Version 1.4

Document No.: BRT_000002 Clearance No.: BRT#004

4.7.7

Touch detection in none-ACTIVE state

When FT81x is in none-ACTIVE state, a touch event can still be detected and reported to the host

through the INT_N pin. In other words, a touch event can wake-up the host if needed.

For resistive touch, the INT_N pin will be asserted low when the screen is touched, regardless of the

setting of the interrupt registers. This will happen when the FT81x is in STANDBY or SLEEP state, but not

in POWERDOWN state.

For capacitive touch, the INT_N pin will follow CTP_INT_N pin when the FT81x is in STANDBY, SLEEP or

POWERDOWN state.

4.8 Power Management

4.8.1

Power supply

The FT81x may be operated with a single supply of 3.3V applied to VCC and VCCIO pins. For operation

with a host MPU/MCU at a lower supply, connect the VCCIO1 to the MPU IO supply to match the interface

voltage. For operation with LCD/touch panels at lower voltages, connect the VCCIO2 to the LCD/touch IO

supply.

Symbol

Typical

Description

VCCIO1

1.8V, or 2.5V, or 3.3V

Supply for Host interface digital I/O pins

VCCIO2

1.8V, or 2.5V, or 3.3V

Supply for RGB and touch interface I/O pins

VCC

3.3V

Supply for 3.3V circuits and internal regulator

VOUT1V2

1.2V

Supply for digital core. Generated by internal regulator

Table 4-19 Power supply

4.8.2

Internal Regulator and POR

The internal regulator provides power to the core circuit. A 47kΩ resistor is recommended to pull the

PD_N pin up to VCCIO1, together with a 100nF capacitor to ground in order to delay the internal

regulator powering up after the VCC and VCCIO are stable.

The internal regulator requires a compensation capacitor to be stable. A typical design requires a 4.7uF

capacitor between the VOUT1V2 and GND pins. Do not connect any other load to the VOUT1V2 pin.

The internal regulator will generate a Power-On-Reset (POR) pulse when the output voltage rises above

the POR threshold. The POR will reset all the core digital circuits.

It is possible to use PD_N pin as an asynchronous hardware reset input. Drive PD_N low for at least 5ms

and then drive it high will reset the FT81x chip.

FT812Q-R Scheda tecnica(PDF) 36 Page - Bridgetek Pte Ltd.

FT812Q-R Scheda tecnica(HTML) 36 Page - Bridgetek Pte Ltd.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63

Scheda tecnica Scarica

Link URL