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XTPS563203DRLR Scheda tecnica(PDF) 10 Page - Texas Instruments

Il numero della parte XTPS563203DRLR
Spiegazioni elettronici  TPS56320x 4.2-V to 17-V Input, 3-A Synchronous Buck Converter in SOT563
PDF  32 Pages
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XTPS563203DRLR Scheda tecnica(HTML) 10 Page - Texas Instruments

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At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal one
shot timer expires. This one shot duration is set proportional to the output voltage, VO, and inversely proportional
to the converter input voltage, VIN, to maintain a pseudo-fixed frequency over the input voltage range, hence
it is called adaptive on-time control. The one-shot timer is reset and the high-side MOSFET is turned on again
when the feedback voltage falls below the reference voltage. An internal ramp is added to reference voltage to
simulate output ripple, eliminating the need for ESR induced output ripple from D-CAP3 control mode.
7.3.2 Eco-mode Control
TPS563203 is designed with advanced Eco-mode to maintain high light load efficiency. As the output current
decreases from heavy load condition, the inductor current is also reduced and eventually comes to point that
its ripple valley touches zero level, which is the boundary between continuous conduction and discontinuous
conduction modes. The rectifying MOSFET is turned off when the zero inductor current is detected. As the load
current further decreases the converter runs into discontinuous conduction mode. The on-time is kept almost the
same as it was in the continuous conduction mode so that it takes longer time to discharge the output capacitor
with smaller load current to the level of the reference voltage. This asction makes the switching frequency lower,
proportional to the load current, and keeps the light load efficiency high. The transition point to the light load
operation IOUT(LL) current can be calculated in Equation 1.
IN
OUT
OUT
OUT(LL)
SW
IN
(V
V
)
V
1
I
2
L
f
V
u
u
u
u
(1)
7.3.3 Soft Start and Pre-Biased Soft Start
TPS56320x have an internal 1.4-ms soft-start. When the EN pin becomes high, the internal soft-start function
begins ramping up the reference voltage to the PWM comparator.
If the output capacitor is pre-biased at start-up, the device initiates switching and start ramping up only after the
internal reference voltage becomes greater than the feedback voltage VFB. This scheme makes sure that the
converters ramp up smoothly into regulation point.
7.3.4 Large Duty Operation
The TPS56320x can support large duty operations up to 95% by smoothly dropping down the switching
frequency. When input voltage Vin < 7 V and VFB is lower than internal reference voltage, the switching
frequency is allowed to smoothly drop to make TON extended to keep output voltage and improve the load
transient performance. The minimum switching frequency is limited to about 200 kHz.
7.3.5 Current Protection
The output overcurrent limit (OCL) is implemented using a cycle-by-cycle valley detect control circuit. The switch
current is monitored during the OFF state by measuring the low-side FET drain to source voltage. This voltage is
proportional to the switch current. To improve accuracy, the voltage sensing is temperature compensated.
During the on time of the high-side FET switch, the switch current increases at a linear rate determined by Vin,
Vout, the on-time and the output inductor value. During the on time of the low-side FET switch, this current
decreases linearly. The average value of the switch current is the load current Iout. If the monitored current is
above the OCL level, the converter maintains low-side FET on and delays the creation of a new set pulse,
even the voltage feedback loop requires one, until the current level becomes OCL level or lower. In subsequent
switching cycles, the on-time is set to a fixed value and the current is monitored in the same manner.
There are some important considerations for this type of overcurrent protection. The load current is higher than
the over-current threshold by one half of the peak-to-peak inductor ripple current. Also, when the current is being
limited, the output voltage tends to fall as the demanded load current can be higher than the current available
from the converter. This even can cause the output voltage to fall. When the FB voltage falls below the UVP
threshold voltage, the UVP comparator detects it. And then, the device shuts down after the UVP delay time
(typically 24 µs) and re-start after the hiccup time (typically 13 ms).
When the overcurrent condition is removed, the output voltage returns to the regulated value.
TPS563203, TPS563206
SLUSEZ4 – MARCH 2023
www.ti.com
10
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Product Folder Links: TPS563203 TPS563206



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