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XTPS563203DRLR Scheda tecnica(PDF) 19 Page - Texas Instruments |
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XTPS563203DRLR Scheda tecnica(HTML) 19 Page - Texas Instruments |
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19 / 32 page ![]() Iout = 2A/div 200us/div Vout = 20mV/div (AC) Figure 8-20. TPS563203 Load Transient with 0.3 A to 2.7 A Iout = 2A/div 200us/div Vout = 20mV/div (AC) Figure 8-21. TPS563206 Load Transient with 0.3 A to 2.7 A 8.3 Power Supply Recommendations TPS56320x are designed to operate from input supply voltages in the range of 4.2 V to 17 V. Buck converters require the input voltage to be higher than the output voltage for proper operation. And the maximum duty is 95%. 8.4 Layout 8.4.1 Layout Guidelines 1. VIN and GND traces must be as wide as possible to reduce trace impedance. The wide areas are also of advantage from the view point of heat dissipation. 2. The input capacitor and output capacitor must be placed as close to the device as possible to minimize trace impedance. 3. Provide sufficient vias for the input capacitor and output capacitor. 4. Keep the SW trace as physically short and wide as practical to minimize radiated emissions. 5. Do not allow switching current to flow under the device. 6. A separate VOUT path must be connected to the upper feedback resistor. 7. Make a Kelvin connection to the GND pin for the feedback path. 8. Voltage feedback loop must be placed away from the high-voltage switching trace, and preferably has ground shield. 9. The trace of the FB node must be as small as possible to avoid noise coupling. 10. The GND trace between the output capacitor and the GND pin must be as wide as possible to minimize its trace impedance. www.ti.com TPS563203, TPS563206 SLUSEZ4 – MARCH 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TPS563203 TPS563206 |
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