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XTPS563203DRLR Scheda tecnica(PDF) 20 Page - Texas Instruments |
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XTPS563203DRLR Scheda tecnica(HTML) 20 Page - Texas Instruments |
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20 / 32 page ![]() 8.4.2 Layout Example VIN SW GND FB EN BST EN Control GND VIN VOUT GND SW L COUT CIN RFBT RFBB VIA (Connected to GND plane at bottom layer) CBST Line at bottom layer VIA (Connected to SW) Figure 8-22. TPS563203 Layout TPS563203, TPS563206 SLUSEZ4 – MARCH 2023 www.ti.com 20 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS563203 TPS563206 |
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