ISL81601 datasheet(38/54 Pages) RENESAS

38 / 54 page

FN9299 Rev.3.1

Page 38 of 53

May 27, 2021

ISL81601

5. Functional Description

5.11

Frequency Synchronization and Dithering

The RT/SYNC pin can synchronize the ISL81601 to an external clock or the CLKOUT/DITHER pin of another

ISL81601. When the RT/SYNC pin is connected to the CLKOUT/DITHER pin of another ISL81601, the two

controllers operate in cascade synchronization with phase interleaving.

When the RT/SYNC pin is connected to an external clock, the ISL81601 synchronizes to this external clock

frequency. The frequency set by the RT resistor can be either lower or higher than, or equal to the external clock

frequency.

The CLKOUT/DITHER pin outputs a clock signal with approximately 300ns pulse width. The signal frequency is

the same as the frequency set by the resistor from the RT pin to ground or the external sync clock. The signal rising

edge phase angle to the rising edge of the internal clock or the external clock to the RT/SYNC pin can be set by the

voltage applied to the FB_IN and IMON_IN pins. The phase interleaving can be implemented by the cascade

connecting of the upper chip CLKOUT/DITHER pin to the lower chip RT/SYNC pin in a parallel system. Table 2

on page 38 shows the CLKOUT/DITHER phase settings with different FB_IN and IMON_IN pin voltages.

When the FB_IN is connected to 5V, the VIN feedback control loop is disabled. When IMON_IN is connected to

5V, the average input current control loop and input current hiccup OCP are disabled.

In multi-chip cascade parallel operation, the CLKOUT pin of the upstream chip is connected to the RT/SYNC pin

of the downstream chip. The BSTEN, FB_IN, SS/TRK, COMP, FB_OUT, IMON_OUT, OV, EN/UVLO,

IMON_IN, and CLKEN pins of all the paralleled chips should be tied together.

The CLKOUT/DITHER pin provides a dual function option. When a capacitor CDITHER is connected on

CLKOUT/DITHER pin, the internal circuit disables the CLKOUT function and enables the DITHER function.

When the CLKOUT/DITHER pin voltage is lower than 1.05V, a typical 8µA current source IDITHERSO charges the

capacitor on the pin. When the capacitor voltage is charged to more than 2.2V, a typical 10µA current source

IDITHERSI discharges the capacitor on the pin. A sawtooth voltage waveform shown in Figure 53 on page 39 is

generated on the CLKOUT/DITHER pin. The internal clock frequency is modulated by the sawtooth voltage on the

CLKOUT/DITHER pin. The clock frequency dither range is set to typically ±15% of the frequency set by the

resistor on RT/SYNC pin. The dither function is lost when the chip is synchronized to an external clock.

Table 2. CLKOUT Phase Shift vs FB_IN and IMON_IN Voltage

CLKOUT Phase Shift

120°

90°

60°

180°

FB_IN Voltage

Active

IMON_IN Voltage

1Active

Active

Note: “1” means logic high 4.7V to 5V. “Active” means logic low 0V to 4.3V.

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