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MPC604 Scheda tecnica(PDF) 4 Page - NXP Semiconductors |
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MPC604 Scheda tecnica(HTML) 4 Page - NXP Semiconductors |
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4 / 32 page ![]() 4 PowerPC 604 RISC Microprocessor Technical Summary Major features of the 604 are as follows: • High-performance, superscalar microprocessor — As many as four instructions can be issued per clock. — As many as six instructions can start executing per clock (including three integer instructions) — Single clock cycle execution for most instructions • Six independent execution units and two register files — BPU featuring dynamic branch prediction – Speculative execution through two branches – 64-entry fully-associative branch target address cache (BTAC) – 512-entry branch history table (BHT) with two bits per entry for four levels of prediction— not-taken, strongly not-taken, taken, strongly taken. — Two single-cycle IUs (SCIUs) and one multiple-cycle IU (MCIU) – Instructions that execute in the SCIU take one cycle to execute; most instructions that execute in the MCIU take multiple cycles to execute. – Each SCIU has a two-entry reservation station to minimize stalls – The MCIU has a two-entry reservation station and provides early exit (three cycles) for 16- x 32-bit and overflow operations. – Thirty-two GPRs for integer operands – Twelve rename buffers for GPRs — Three-stage floating-point unit (FPU) – Fully IEEE 754-1985 compliant FPU for both single- and double-precision operations – Supports non-IEEE mode for time-critical operations – Fully pipelined, single-pass double-precision design – Hardware support for denormalized numbers – Two-entry reservation station to minimize stalls – Thirty-two 64-bit FPRs for single- or double-precision operands — Load/store unit (LSU) – Two-entry reservation station to minimize stalls – Single-cycle, pipelined cache access – Dedicated adder performs EA calculations – Performs alignment and precision conversion for floating-point data – Performs alignment and sign extension for integer data – Four-entry finish load queue (FLQ) provides load miss buffering – Six-entry store queue – Supports both big- and little-endian modes • Rename buffers — Twelve GPR rename buffers — Eight FPR rename buffers Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com AR CH IVE D B Y F RE ES CA LE SE MI CO ND UC TO R, INC . |
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