PowerPC 604 RISC Microprocessor Technical Summary

13

Figure 4. System Interface

Four-beat burst-read memory operations that load an eight-word cache block into one of the on-chip caches

are the most common bus transactions in typical systems, followed by burst-write memory operations, I/O

controller interface operations, and single-beat (noncacheable or write-through) memory read and write

operations. Additionally, there can be address-only operations, variants of the burst and single-beat

operations (global memory operations that are snooped and atomic memory operations, for example), and

address retry activity (for example, when a snooped read access hits a modified line in the data cache).

Memory accesses can occur in single-beat or four-beat burst data transfers. The address and data buses are

independent for memory accesses to support pipelining and split transactions. The 604 supports bus

pipelining and out-of-order split-bus transactions. In general, the bus-pipelining mechanism allows as many

as three address tenures to be outstanding before a data tenure is initiated. Address tenures for address-only

transactions can exceed this limit.

Typically, memory accesses are weakly-ordered. Sequences of operations, including load/store string/

multiple instructions, do not necessarily complete in the same order in which they began—maximizing the

efficiency of the bus without sacrificing coherency of the data. The 604 allows load operations to precede

store operations (except when a dependency exists, of course). In addition, the 604 provides a separate

queue for snoop push operations so these operations can access the bus ahead of previously queued

operations. The 604 dynamically optimizes run-time ordering of load/store traffic to improve overall

performance.

In addition, the 604 implements a data bus write-only signal (DBWO) that can be used for reordering write

operations. Asserting DBWO causes the first write operation to occur before any read operations on a given

processor. Although this may be used with any write operations, it can also be used to reorder a snoop push

operation.

Access to the system interface is granted through an external arbitration mechanism that allows devices to

compete for bus mastership. This arbitration mechanism is flexible, allowing the 604 to be integrated into

systems that use various fairness and bus-parking procedures to avoid arbitration overhead. Additional

multiprocessor support is provided through coherency mechanisms that provide snooping, external control

of the on-chip caches and TLBs, and support for a secondary cache. The PowerPC architecture provides the

load/store with reservation instruction pair (lwarx/stwcx.) for atomic memory references and other

operations useful in multiprocessor implementations.

The following sections describe the 604 bus support for memory and I/O controller interface operations.

Note that some signals perform different functions depending upon the addressing protocol used.

PowerPC

604

Processor

ADDRESS

ADDRESS ARBITRATION

ADDRESS START

ADDRESS TRANSFER

TRANSFER ATTRIBUTE

ADDRESS TERMINATION

CLOCKS

DATA

DATA ARBITRATION

DATA TRANSFER

DATA TERMINATION

PROCESSOR STATE

TEST AND CONTROL

+3.3 V

Freescale Semiconductor, Inc.

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Go to: www.freescale.com

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