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PowerPC 604 RISC Microprocessor Technical Summary

The MCIU consists of a 32-bit integer multiplier/divider. The multiplier supports early exit on 16- x 32-bit

operations, and is responsible for executing the mfspr and mtspr instructions, which are used to read and

write special-purpose registers. Note that the load and store instructions that update their address base

register (specified by the rA operand) pass the update results on the MCIU’s result bus. Otherwise, the

MCIU’s result bus is dedicated to MCIU operations. (This option is indicated by specifying a period at the

end of the instruction mnemonic).

1.2.2.2 Floating-Point Unit (FPU)

The FPU, shown in Figure 1 and Figure 2, is a single-pass, double-precision execution unit; that is, both

single- and double-precision operations require only a single pass, with a latency of three cycles.

As the decode/dispatch unit issues instructions to the FPU’s two reservation stations, source operand data

may be accessed from the FPRs, the floating-point rename buffers, or the result buses. Results in turn are

written to the floating-point rename buffers and to the reservation stations and are made available to

subsequent instructions. Instructions are executed from the reservation station in dispatch order.

1.2.2.3 Load/Store Unit (LSU)

The LSU, shown in Figure 1 and Figure 2, transfers data between the data cache and the result buses, which

route data to other execution units. The LSU supports the address generation and handles any alignment for

transfers to and from system memory. The LSU also supports cache control instructions and load/store

multiple/string instructions. As noted above, load and store instructions that update the base address register

pass their results on the MCIU’s result bus. This is the only exception to the dedicated use of result buses.

The LSU includes a 32-bit adder dedicated for EA calculation. Data alignment logic manipulates data to

support aligned or misaligned transfers with the data cache. The LSU’s load and store queues are used to

buffer instructions that have been executed and are waiting to be completed. The queues are used to monitor

data dependencies generated by data forwarding and out-of-order instruction execution ensuring a

sequential model.

The LSU allows load operations to precede pending store operations and resolves any dependencies

incurred when a pending store is to the same address as the load. If such a dependency exists, the LSU delays

the load operation until the correct data can be forwarded. If only the low-order 12 bits of the EAs match,

both addresses may be aliases for the same physical address, in which case, the load operation is delayed

until the store has been written back to the cache, ensuring that the load operation retrieves the correct data.

The LSU does not allow the following operations to be speculatively performed on unresolved branches:

•

Store operations

•

Loading of noncacheable data or cache miss operations

•

Loading from I/O controller interface segments

1.2.3 Memory Management Units (MMUs)

The primary functions of the MMUs are to translate logical (effective) addresses to physical addresses for

memory accesses, I/O accesses (most I/O accesses are assumed to be memory-mapped), and I/O controller

interface accesses, and to provide access protection on blocks and pages of memory.

The PowerPC MMUs and exception model support demand-paged virtual memory. Virtual memory

management permits execution of programs larger than the size of physical memory; demand-paged implies

that individual pages are loaded into physical memory from system memory only when they are first

accessed by an executing program.

Freescale Semiconductor, Inc.

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