MB91301 datasheet(53/135 Pages) FUJI

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MB91301 Series

• Instruction Cache Tags

[bit 31 to bit 9] Address tag

The address tag stores the upper 23 bits of the memory address of the instruction cached in the corresponding

block.

For example, memory address IA of the instruction data stored in sub-block k in block i is obtained from the

following equation:

= address tag × 29 + i × 24 + k × 22

The address tag is used to check for a match with the instruction address requested for access by the CPU.

The CPU and cache behave as follows depending on the result of the tag check:

• When the requested instruction data exists in the cache (hit), the cache transfers the data to the CPU within

the cycle.

• When the requested instruction data does not exist in the cache (miss), the CPU and cache obtain the data

loaded by external access at the same time.

[bit 7 to bit4] SBV3 to SBV0 : Sub-block validation

When SBVn contains "1", the corresponding sub-block holds the current instruction data at the address located

by the tag. Each sub-block usually holds two instructions (excluding immediate-value transfer instructions).

[bit 3] TAGV : Tag validation bit

This bit indicates whether the address tag value is valid. When the bit contains "0", the corresponding block is

invalid regardless of the settings of the sub-block validation bits. (The bit is set to "0" when the cache is flushed.)

[bit 1] LRU (only in way 1)

This bit exists only in the instruction cache tag in way 1. The bit indicates way 1 or 2 as the way containing the

last entry accessed in the selected set. When set to "1", the LRU bit indicates that the entry of the set in way 1

is the last entry accessed. When set to "0", it indicates that the one in way 2 is the last entry accessed.

[bit 0] ETLK : Entry lock

This bit is used to lock all the entries in the block corresponding to the tag in the cache. When the ETLK bit is

set to "1", the entries are locked and are not updated when a cache miss occurs. Note, however, that invalid

sub-blocks are updated. If a cache miss occurs with both of ways 1 and 2 in the entry lock states, access to

external memory takes place after losing one cycle used for evaluating the cache miss.

SBV2

SBV3

SBV1

SBV0

TAGV

LRU

ETLK

SBV2

SBV3

SBV1

SBV0

TAGV

ETLK

Address tag

Way 1

Way 2

Address tag

Vacancy

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