MPC5553AVF80R2 datasheet(39/60 Pages) FREESCALE

39 / 60 page

Electrical Characteristics

MPC5553 Microcontroller Data Sheet, Rev. 0

Preliminary—Subject to Change Without Notice

Freescale Semiconductor

Figure 18. DSPI Classic SPI Timing — Master, CPHA = 0

Data Valid (after SCK edge)

Master (MTFE = 0)

Slave

Master (MTFE = 1, CPHA=0)

Master (MTFE = 1, CPHA=1)

tSUO

—

Data Hold Time for Outputs

Master (MTFE = 0)

Slave

Master (MTFE = 1, CPHA = 0)

Master (MTFE = 1, CPHA = 1)

tHO

–5

5.5

–5

—

–5

5.5

–5

—

–5

5.5

–5

—

1 DSPI timing specified at VDD = 1.35V to 1.65V, VDDEH = 3.0V to 5.5V, VDD33 and VDDSYN = 3.0V to 3.6V, T

A = TL to TH,

and CL = 50pF with SRC = 0b11.

2 The minimum SCK Cycle Time restricts the baud rate selection for given system clock rate. These numbers are calculated

based on two MPC55xx devices communicating over a DSPI link.

3 The actual minimum SCK Cycle Time is limited by pad performance.

4 The maximum value is programmable in DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]

5 The maximum value is programmable in DSPI_CTARx[PASC] and DSPI_CTARx[ASC]

6 This number is calculated assuming the SMPL_PT bit field in DSPI_MCR is set to 0b10.

Table 26. DSPI Timing1 (continued)

Num

Characteristic

Symbol

80 MHz

112 MHz

132 MHz

Unit

Min

Max

Min

Max

Min

Max

Data

Last Data

First Data

Data

Last Data

SIN

SOUT

PCSx

SCK Output

(CPOL=0)

(CPOL=1)

MPC5553AVF80R2 Scheda tecnica(PDF) 39 Page - Freescale Semiconductor, Inc

MPC5553AVF80R2 Scheda tecnica(HTML) 39 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Scheda tecnica Scarica

Link URL