MPC5553AVF80R2 datasheet(19/60 Pages) FREESCALE

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Electrical Characteristics

MPC5553 Microcontroller Data Sheet, Rev. 0

Preliminary—Subject to Change Without Notice

Freescale Semiconductor

3.9

Oscillator & FMPLL Electrical Characteristics

Table 12. HiP7 FMPLL Electrical Specifications

(VDDSYN = 3.0V to 3.6 V, VSS = VSSSYN = 0 V, TA = TL to TH)

Num

Characteristic

Symbol

Min.

Value

Max.

Value

Unit

PLL Reference Frequency Range:

Crystal reference

External reference

Dual Controller (1:1 mode)

fref_crystal

fref_ext

fref_1:1

fsys/2

MHz

System Frequency 1

fsys

fico(min) ÷ 2

RFD

fMAX

MHz

System Clock Period

tCYC

—1 / fsys

Loss of Reference Frequency 3

fLOR

100

1000

kHz

Self Clocked Mode (SCM) Frequency 4

fSCM

7.4

17.5

MHz

EXTAL Input High Voltage

Crystal Mode 5

All other modes (Dual Controller (1:1),

Bypass, External Reference)

VIHEXT

Vxtal + 0.4v

((VDDE5/2) + 0.4v)

—

EXTAL Input Low Voltage

Crystal Mode 6

All other modes (Dual Controller (1:1),

Bypass, External Reference)

VILEXT

—

Vxtal – 0.4v

((VDDE5/2) – 0.4v)

XTAL Current 7

IXTAL

0.8

Total On-chip stray capacitance on XTAL

CS_XTAL

—1.5

Total On-chip stray capacitance on EXTAL

CS_EXTAL

—1.5

Crystal manufacturer’s recommended

capacitive load

See crystal

specification

See crystal

specification

Discrete load capacitance to be connected

to EXTAL

CL_EXTAL

—2*CL – CS_EXTAL –

CPCB_EXTAL

Discrete load capacitance to be connected

to XTAL

CL_XTAL

—2*CL – CS_XTAL –

CPCB_XTAL

PLL Lock Time9

tlpll

—750

µs

Dual Controller (1:1) Clock Skew (between

CLKOUT and EXTAL) 10, 11

tskew

–2

Duty Cycle of reference

tdc

Frequency un-LOCK Range

fUL

– 4.0

4.0

% fsys

Frequency LOCK Range

fLCK

– 2.0

2.0

% fsys

CLKOUT Period Jitter,12, 13

Measured at fSYS Max

Peak-to-peak Jitter

(Clock edge to clock edge)

Long Term Jitter

(Averaged over 2 ms interval)

Cjitter

—

5.0

.01

% fclkout

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