MPC5553AVF80R2 datasheet(10/60 Pages) FREESCALE

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MPC5553 Microcontroller Data Sheet, Rev. 0

Preliminary—Subject to Change Without Notice

Electrical Characteristics

Freescale Semiconductor

3.6

VRC/POR Electrical Specifications

Table 6. VRC/POR Electrical Specifications

Num

Characteristic

Symbol

Min

Max

Units

1.5V (VDD) POR Negated (Ramp Up)

1.5V (VDD) POR Asserted (Ramp Down)

V_POR15

1.1

1.35

3.3V (VDDSYN) POR Negated (Ramp Up)

3.3V (VDDSYN) POR Asserted (Ramp Down)

V_POR33

2.0

2.85

RESET Pin Supply (VDDEH6) POR Negated (Ramp Up)

RESET Pin Supply (VDDEH6) POR Asserted (Ramp Down)

V_POR5

2.0

2.85

VRC33 voltage before regulator controller allows the pass transistor

to start turning on

V_TRANS_

START

1.0

2.0

VRC33 voltage when regulator controller allows the pass transistor

to completely turn on1, 2

1 User must be able to supply full operating current for the 1.5V supply when the 3.3V supply reaches this range.

2 Current limit may be reached during ramp up and should not be treated as short circuit current.

V_TRANS_ON

2.0

2.85

VRC33 voltage above which the regulator controller will keep the

1.5V supply in regulation3, 4

3 At peak current for device.

4 Assumes that the Freescale recommended board requirements and transistor recommendations are met. Board signal

traces/routing from the VRCCTL package signal to the base of the external pass transistor and between the emitter of the pass

transistor to the VDD package signals should have a maximum of 100 nH inductance and minimal resistance (<1 ohm).

VRCCTL should have a nominal 1

µF phase compensation capacitor to ground. VDD should have a 20 µF (nominal) bulk

capacitor (> 4

µF over all conditions, including lifetime). High frequency bypass capacitors consisting of eight 0.01 µF, two 0.1

µF, and one 1 µF capacitors should be place around the package on the VDD supply signals.

V_VRC33REG

3.0

—

Current which can be sourced by VRCCTL

I_VRCCTL5

5 I_VRCCTL measured at the following conditions: VDD=1.35V, VRC33=3.1V, V_VRCCTL=2.2V.

– 40C

11.0

—

25C

9.0

—

150C (Tj)

7.5

—

Voltage differential during power up that VDD33 can lag VDDSYN or

VDDEH6 before VDDSYN and VDDEH6 reach V_POR33 and

V_POR5 minimums respectively

VDD33_LAG

—

1.0

Absolute value of Slew Rate on power supply pins

—

V/ms

Required Gain:

Idd / I_VRCCTL (@vdd = 1.35v, fsys = 132MHz)

4, 6

6 Values are based on IDD from high use applications as explained in the IDD Electrical Specification.

BETA7

7 BETA is measured on a per part basis and is calculated as IDD / I_VRCCTL and represents the worst case external transistor

BETA.

– 40C

55.08

8 Preliminary value. Final specification pending characterization.

——

25C

58.08

——

150C (Tj)

70.08

500

—

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