ADRF5080BCCZN-R7 datasheet(13/15 Pages) AD

13 / 15 page

Data Sheet

ADRF5080

THEORY OF OPERATION

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Rev. 0 | 13 of 15

The ADRF5080 integrates a driver to perform logic function inter-

nally and to provide the advantage of a simplified CMOS-/LVTTL-

compatible control interface. The driver features five digital control

input pins (LS, EN, V1, V2, and V3) that control the state of the RFx

paths (see Table 7).

The LS input allows the user to define the control input logic

sequence for the RF path selections. The logic level applied to the

V1, V2, and V3 pins determine which RF port is in the insertion loss

state while the other three paths are in the isolation state.

When the EN pin is logic low, the logic level applied to the CMOS

control input pin determines which RF port is in the insertion loss

state and which RF port is in the isolation state. The insertion loss

path conducts the RF signal between the selected RF throw port

and the RF common port. The isolation path provides high loss

between the insertion loss path and the unselected RF throw port.

The unselected RF port of the ADRF5080 is reflective.

When the EN pin is logic high, the switch is in an all off state

regardless of the logic state of the LS, V1, V2 and V3 pins, and all

of the RFx to RFC path is in an isolation state.

RF INPUT AND OUTPUT

All of the RF ports (RFC, RF1 to RF8) are DC-coupled to 0 V,

and no DC blocking is required at the RF ports when the RF line

potential is equal to 0 V. The RF ports are internally matched to 50

Ω. Therefore, external matching networks are not required.

The switch design is bidirectional with equal power handling capa-

bilities. The RF input signal can be applied to the RFC port or the

selected RF throw port.

POWER SUPPLY

The ADRF5080 requires a positive supply voltage applied to the

VDD pin and a negative supply voltage applied to the VSS pin.

Bypassing capacitors are recommended on the supply lines to

minimize RF coupling.

The ideal power-up sequence is as follows:

1. Connect GND to ground.

2. Power up VDD and VSS. Powering up VSS after VDD avoids

current transients on VDD during ramp up.

3. Apply a control voltage to the digital control inputs (EN, LS, V1,

V2, and V3). Applying a control voltage to the digital control

inputs before the VDD supply can inadvertently forward bias

and damage the internal ESD protection structures. Use a

series 1 kΩ resistor to limit the current flowing into the control

pin in such cases. If the control pins are not driven to a valid

logic state (that is, controller output is in high impedance state)

after VDD is powered up, it is recommended to use a pull-up or

pull-down resistor.

4. Apply an RF input signal.

The ideal power-down sequence is the reverse order of the power-

up sequence.

SINGLE-SUPPLY OPERATION

The ADRF5080 can operate with a single positive supply voltage

applied to the VDD pin and VSS pin connected to ground. However,

some performance degradations can occur in the input compres-

sion and input third-order intercept.

Table 7. Control Voltage Truth Table

Digital Control Inputs

RFx Paths

RF1 to RFC RF2 to RFC RF3 to RFC RF4 to RFC RF5 to RFC RF6 to RFC

RF7 to RFC RF8 to RFC

Low

Off

Low

High

Off

Low

High

Low

Off

Low

High

Off

Low

High

Low

Off

Low

High

Low

High

Off

Low

High

Low

Off

Low

High

Off

Low

High

Low

Off

Low

High

Low

High

Off

Low

High

Low

High

Low

Off

Low

High

Low

High

Off

Low

High

Low

Off

Low

High

Low

High

Off

Low

High

Low

Off

Low

High

Off

High

Low or

high

Low or

high

Low or

high

Low or

high

Off

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