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ADRF5080BCCZN-R7 Scheda tecnica(PDF) 14 Page - Analog Devices |
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ADRF5080BCCZN-R7 Scheda tecnica(HTML) 14 Page - Analog Devices |
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14 / 15 page ![]() Data Sheet ADRF5080 APPLICATIONS INFORMATION analog.com Rev. 0 | 14 of 15 The ADRF5080 has two power supply pins (VDD and VSS) and five digital control pins (LS, EN, V1, V2, and V3). Figure 27 shows the external components and connections for the supply and control pins. Supply and control pins are decoupled with a 10 pF or 100 pF multilayer ceramic capacitor. The device pinout allows the place- ment of the decoupling capacitors close to the device. No other external components are needed for bias and operation, except DC blocking capacitors on the RFx pins when the RF lines are biased at a voltage different than 0 V. Refer to Pin Configuration and Function Descriptions section for further details. Figure 27. Recommended Schematic RECOMMENDATIONS FOR PCB DESIGN The RF ports are matched to 50 Ω internally and the pinout is designed to mate a coplanar waveguide (CPWG) with 50 Ω charac- teristic impedance on the PCB. Figure 28 shows the referenced CPWG RF trace design for an RF substrate with 8 mil thick Rogers RO4003 dielectric material. The RF trace with a 14 mil width and a 7 mil clearance is recommended for 2.8 mil finished copper thickness. Figure 28. Example PCB Stackup Figure 29 shows the routing of the RF traces, supply, and control signals from the device. The ground planes are connected with as many filled through vias as allowed for optimal RF and thermal performance. The primary thermal path for the device is the bottom side. Figure 29. PCB Routings Figure 30 shows the recommended layout from the device RFx pins to the 50 Ω CPWG on the referenced stackup. PCB pads are drawn 1:1 to device pads. The ground pads are drawn solder mask defined, and the signal pads are drawn as pad defined. The RF trace from the PCB pad is extended with the same width by 2 mils and tapered to an RF trace with 45° angle. The paste mask is also designed to match the pad without any aperture reduction. The paste is divided into multiple openings for the paddle. Figure 30. Recommended RFx Pin Transitions For alternate PCB stackups with different dielectric thickness and CPWG design, contact Analog Devices, Inc., Technical Support Request for further recommendations. |
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