AD9985ASLASHPCB datasheet(28/32 Pages) AD

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AD9985A

Rev. 0 | Page 28 of 32

Table 46. Control of the Sync Block Muxes via the Serial Register

Mux No.

Serial Bus Control Bit

Control Bit State

Result

1 and 2

0x0E: Bit 3

Pass Hsync

Pass sync-on-green

0x0F: Bit 5

Pass Coast

Pass Vsync

0x0E: Bit 0

Pass Vsync

Pass sync separator signal

SYNC SLICER

The purpose of the sync slicer is to extract the sync signal from

the green graphics channel. A sync signal is not present on all

graphics systems, only those with sync-on-green. The sync

signal is extracted from the green channel in a two-step process.

First, the SOG input is clamped to its negative peak (typically,

0.3 V below the black level). Next, the signal goes to a compara-

tor with a variable trigger level, nominally 0.15 V above the

clamped level. The sliced sync is typically a composite sync

signal containing both Hsync and Vsync.

SYNC SEPARATOR

A sync separator extracts the Vsync signal from a composite

sync signal. It does this through a low-pass filter-like or

integrator-like operation. It works on the idea that the Vsync

signal stays active for a much longer time than the Hsync signal,

so it rejects any signal shorter than a threshold value, which is

somewhere between an Hsync pulse width and a Vsync pulse

width.

The sync separator on the AD9985A is simply an 8-bit digital

counter with a 5 MHz clock. It works independently of the

polarity of the composite sync signal. (Polarities are determined

elsewhere on the chip.) The basic idea is that the counter counts

up when Hsync pulses are present. But since Hsync pulses are

relatively short in width, the counter only reaches a value of N

before the pulse ends. It then starts counting down, eventually

reaching 0 before the next Hsync pulse arrives.

The specific value of N varies for different video modes, but is

always less than 255. For example, with a 1 μs width Hsync, the

counter only reaches 5 (1 μs/200 ns = 5). Now, when Vsync is

present on the composite sync, the counter also counts up.

However, since the Vsync signal is much longer, it counts to a

higher number M. For most video modes, M is at least 255. So,

Vsync can be detected on the composite sync signal by

detecting when the counter counts to a value higher than N.

The specific count that triggers detection (T) can be

programmed through the serial register (0x11).

Once Vsync has been detected, there is a similar process to

detect when it goes inactive. At detection, the counter first

resets to 0, then starts counting up when Vsync goes away.

Similar to the previous case, it detects the absence of Vsync

when the counter reaches the threshold count (T). In this way, it

rejects noise and/or serration pulses. Once Vsync is detected to

be absent, the counter resets to 0 and begins the cycle again.

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