AD9985ASLASHPCB datasheet(22/32 Pages) AD

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AD9985A

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Table 16. Active Hsync Override Settings

Override

Result

Autodetermines the active interface (power-up

default)

Override, Bit 3 determines the active interface

Active Hsync Select

This bit is used under two conditions. It is used to

select the active Hsync when the override bit is set

(Bit 4). Alternately, it is used to determine the active

Hsync when not overriding, but both Hsyncs are

detected.

Table 17. Active Hsync Select Settings

Select

Result

Hsync input (power-up default)

Sync-on-green input

Vsync Output Invert

This bit inverts the polarity of the Vsync output

Table 18 shows the effect of this option.

Table 18. Vsync Output Invert Settings

Invert

Vsync Output

Invert (power-up default)

No invert

Active Vsync Override

This bit is used to override the automatic Vsync

selection. To override, set this bit to Logic 1. When

overriding, the active interface is set via Bit 0 in this

Table 19. Active Vsync Override Settings

Override

Result

Autodetermines the active Vsync (power-up default)

Override, Bit 0 determines the active Vsync

Active Vsync Select

This bit is used to select the active Vsync when the

override bit is set (Bit 1).

Table 20. Active Vsync Select Settings

Select

Result

Vsync input (power-up default)

Sync separator output

Clamp Input Signal Source

This bit determines the source of clamp timing.

Table 21. Clamp Input Signal Source Settings

Clamp Function

Result

Internally generated clamp signal (power-

up default)

Externally provided clamp signal

A 0 enables the clamp timing circuitry controlled by

clamp placement and clamp duration. The clamp

position and duration is counted from the leading

edge of Hsync.

A 1 enables the external CLAMP input pin. The three

channels are clamped when the clamp signal is active.

The polarity of clamp is determined by the clamp

polarity bit (Register 0x0F, Bit 6).

Clamp Input Signal Polarity

This bit determines the polarity of the externally

provided clamp signal.

Table 22. Clamp Input Signal Polarity Settings

Clamp Function

Result

Active low (power-up default)

Active high

Logic 1 means that the circuit clamps when CLAMP is

low, and it passes the signal to the ADC when CLAMP

is high.

Logic 0 means that the circuit clamps when CLAMP is

high, and it passes the signal to the ADC when

CLAMP is low.

Coast Select

This bit is used to select the active Coast source. The

choices are the COAST input pin or Vsync. If Vsync is

selected, the additional decision to use the Vsync

input pin or the output from the sync separator needs

to be made (Register 0x0E, Bits 1, 0).

Table 23. Power-Down Settings

Power-Down

Result

COAST input pin

Vsync (See the Coast Select section)

Coast Input Polarity Override

This register is used to override the internal circuitry

that determines the polarity of the Coast signal going

into the PLL.

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