AD9985ASLASHPCB datasheet(23/32 Pages) AD

23 / 32 page

AD9985A

Rev. 0 | Page 23 of 32

Table 24. Coast Input Polarity Override Settings

Override

Result

Determined by chip (power-up default)

Determined by user

Coast Input Polarity

This bit indicates the polarity of the Coast signal that

is applied to the PLL COAST input.

Table 25. Coast Input Polarity Settings

Coast Polarity

Result

Active low

Active high (power-up default)

Active low means that the clock generator ignores

Hsync inputs when Coast is low, and continues

operating at the same nominal frequency until Coast

goes high.

Active High means that the clock generator ignores

Hsync inputs when Coast is high, and continues

operating at the same nominal frequency until Coast

goes low.

This function needs to be used along with the Coast

polarity override bit (Bit 4).

Seek Mode Override

This bit is used to either allow or disallow the low

power mode. The low power mode (seek mode)

occurs when there are no signals on any of the Sync

inputs.

Table 26. Seek Mode Override Settings

Override

Result

Allow seek mode (power-up default)

Disallow seek mode

PWRDN

This bit is used to put the chip in full power-down. See

the Power Management section for details on which

blocks are powered down.

Table 27. Power-Down Settings

Power-Down

Result

Power-down

Normal operation

7-3

Sync-on-Green Slicer Threshold

This register allows the comparator threshold of the

sync-on-green slicer to be adjusted. This register

adjusts it in steps of 10 mV, with the minimum setting

equaling 10 mV (11111) and the maximum setting

equaling 330 mV (00000).

The default setting is 23, which corresponds to a

threshold value of 100 mV; for a threshold of 150 mV,

the setting should be 18.

Red Clamp Select

This bit determines whether the red channel is

clamped to ground or to midscale. For RGB video, all

three channels are referenced to ground. For YCbCr

(or YUV), the Y channel is referenced to ground, but

the CbCr channels are referenced to midscale.

Clamping to midscale actually clamps to Pin 37.

Table 28. Red Clamp Select Settings

Clamp

Result

Clamp to ground (power-up default)

Clamp to midscale (Pin 37)

Green Clamp Select

This bit determines whether the green channel is

clamped to ground or to midscale.

Table 29. Green Clamp Select Settings

Clamp

Result

Clamp to ground (power-up default)

Clamp to midscale (Pin 37)

Blue Clamp Select

This bit determines whether the blue channel is

clamped to ground or to midscale.

Table 30. Blue Clamp Select Settings

Clamp

Result

Clamp to ground (power-up default)

Clamp to midscale (Pin 37)

7–0

Sync Separator Threshold

This register is used to set the responsiveness of the

sync separator. It sets the number of internal 5 MHz

clock periods the sync separator must count to before

toggling high or low. It works like a low-pass filter to

ignore Hsync pulses in order to extract the Vsync

signal. This register should be set to some number

greater than the maximum Hsync pulse width. The

sync separator threshold uses an internal dedicated

clock with a frequency of approximately 5 MHz.

The default for this register is 32.

7–0

Pre-Coast

This register allows the Coast signal to be applied

prior to the Vsync signal. This is necessary in cases

where pre-equalization pulses are present. The step

size for this control is one Hsync period.

The default is 0.

7–0

Post-Coast

This register allows the Coast signal to be applied

following the Vsync signal. This is necessary when

post-equalization pulses are present. The step size for

this control is one Hsync period.

The default is 0.

AD9985A/PCB Scheda tecnica(PDF) 23 Page - Analog Devices

AD9985A/PCB Scheda tecnica(HTML) 23 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Scheda tecnica Scarica

Link URL