AD9985A

Rev. 0 | Page 10 of 32

Pin

Description

Data Outputs

RED

Data Output, Red Channel.

GREEN

Data Output, Green Channel.

BLUE

Data Output, Blue Channel. The main data outputs. Bit 7 is the MSB. The delay from pixel sampling time to output

is fixed. When the sampling time is changed by adjusting the phase register, the output timing is shifted as well.

The DATACK and HSOUT outputs are also moved, so the timing relationship among the signals is maintained. For

exact timing information, refer to Figure 9, Figure 10, and Figure 11.

Data Clock Output

DATACK

Data Output Clock. This is the main clock output signal used to strobe the output data and HSOUT into external

logic. It is produced by the internal clock generator and is synchronous with the internal pixel sampling clock.

When the sampling time is changed by adjusting the phase register, the output timing is shifted as well. The Data,

DATACK, and HSOUT outputs are all moved, so the timing relationship among the signals is maintained.

References

REF BYPASS

Internal Reference Bypass. Bypass for the internal 1.25 V band gap reference. It should be connected to ground

through a 0.1 μF capacitor. The absolute accuracy of this reference is ±4%, and the temperature coefficient is ±50

ppm, which is adequate for most AD9985A applications. If higher accuracy is required, an external reference can

be used instead.

MIDSCV

Midscale Voltage Reference Bypass. Bypass for the internal midscale voltage reference. It should be connected to

ground through a 0.1 μF capacitor. The exact voltage varies with the gain setting of the blue channel.

FILT

External Filter Connection. For proper operation, the pixel clock generator PLL requires an external filter. Connect

the filter shown in Figure 6 to this pin. For optimal performance, minimize noise and parasitics on this node.

Power Supply

Main Power Supply. These pins supply power to the main elements of the circuit. They should be filtered and kept

as quiet as possible.

Digital Output Power Supply. A large number of output pins (up to 25) switching at high speed (up to 110 MHz)

special care can be taken to minimize output noise transferred into the sensitive analog circuitry. If the AD9985A

compatibility.

Clock Generator Power Supply. The most sensitive portion of the AD9985A is the clock generation circuitry. These

pins provide power to the clock PLL and help the user design for optimal performance. The designer should

provide quiet, noise-free power to these pins.

GND

Ground. The ground return for all circuitry on-chip. It is recommended that the AD9985A be assembled on a

single solid ground plane, with careful attention given to ground current paths.

Serial Port (2-Wire)

SDA

Serial Port Data I/O.

SCL

Serial Port Data Clock.

A0

Serial Port Address Input 1. For a full description of the 2-wire serial register and how it works, refer to the 2-Wire

Serial Control Port section.