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AT87C5103-ICSIL Scheda tecnica(PDF) 24 Page - ATMEL Corporation |
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AT87C5103-ICSIL Scheda tecnica(HTML) 24 Page - ATMEL Corporation |
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24 / 64 page ![]() 24 AT8xC5103 4134C–8051–09/04 Figure 14. SPI Interrupt Requests Generation Registers There are three registers in the module that provide control, status and data storage functions. These registers are describes in the following paragraphs. Serial Peripheral Control Register (SPCON) The Serial Peripheral Control Register does the following: • Selects one of the Master clock rates • Configure the SPI module as Master or Slave • Selects serial clock polarity and phase • Enables the SPI module • Frees the SS pin for a general purpose Table 11 describes this register and explains the use of each bit. SSDIS MODF CPU Interrupt Request SPI Receiver/Error CPU Interrupt Request SPI Transmitter SPI CPU Interrupt Request SPIF Table 11. SPCON Register: Serial Peripheral Control Register - SPCON (S:C3h) 76 543210 SPR2 SPEN SSDIS MSTR CPOL CPHA SPR1 SPR0 Bit Number Bit Mnemonic R/W Mode Description 7 SPR2 R/W Serial Peripheral Rate 2 Bit with SPR1 and SPR0 define the clock rate 6SPEN R/W Serial Peripheral Enable Clear to disable the SPI interface (internal reset of the SPI) Set to enable the SPI interface 5 SSDIS R/W SS Disable Clear to enable SS in both Master and Slave Modes Set to disable SS in both Master and Slave Modes. In Slave Mode, this bit has no effect if CPHA = "0" 4MSTR R/W Serial Peripheral Master Clear to configure the SPI as a Slave Set to configure the SPI as a Master 3CPOL R/W Clock Polarity Clear to have the SCK set to ‘0’ in idle state Set to have the SCK set to ’1’ in idle low 2CPHA R/W Clock Phase Clear to have the data sampled when the SPSCK leaves the idle state (see CPOL) Set to have the data sampled when the SPSCK returns to idle state (see CPOL) 1 SPR1 R/W Serial Peripheral Rate (SPR2:SPR1:SPR0) 000: N.A. 001: FCLK PERIPH /4 010: FCLK PERIPH /8 011: FCLK PERIPH /16 |
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