DSP56362P datasheet(32/152 Pages) FREESCALE

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Phase Lock Loop (PLL) Characteristics

DSP56362 Technical Data, Rev. 4

3-6

Freescale Semiconductor

3.8

Phase Lock Loop (PLL) Characteristics

CLKOUT rising edge from EXTAL rising edge with PLL

enabled (MF = 1, PDF = 1, Ef > 15 MHz)4, 5

CLKOUT falling edge from EXTAL rising edge with PLL

enabled (MF = 2 or 4, PDF = 1, Ef > 15 MHz)4, 5

CLKOUT falling edge from EXTAL falling edge with PLL

enabled (MF

≤ 4, PDF ≠ 1, Ef / PDF > 15 MHz)4, 5

0.0 ns

1.8 ns

Instruction cycle time = ICYC = TC

See

Table 3-5 (46.7%–53.3% duty cycle)

• With PLL disabled

• With PLL enabled

ICYC

0.00 ns

∞

8.53

µs

8.53

µs

1 Measured at 50% of the input transition.

2 The maximum value for PLL enabled is given for minimum V

CO and maximum MF.

3 The indicated duty cycle is for the specified maximum frequency for which a part is rated. The minimum clock high or low

time required for correction operation, however, remains the same at lower operating frequencies; therefore, when a lower

clock frequency is used, the signal symmetry may vary from the specified duty cycle as long as the minimum high time and

low time requirements are met.

4 Periodically sampled and not 100% tested.

5 The skew is not guaranteed for any other MF value.

6 The maximum value for PLL enabled is given for minimum V

CO and maximum DF.

Table 3-6 PLL Characteristics

Characteristics

100 MHz

Unit

Min

Max

VCO frequency when PLL enabled (MF × Ef × 2/PDF)

200

MHz

PLL external capacitor (PCAP pin to VCCP) (CPCAP)

•@ MF

≤ 4

• @ MF > 4

1 CPCAP is the value of the PLL capacitor (connected between the PCAP pin and VCCP). The recommended value in pF for

CPCAP can be computed from one of the following equations:

(680

× MF) – 120, for MF ≤ 4, or

1100

× MF, for MF > 4

(MF

× 580) − 100

× 830

(MF

× 780) − 140

× 1470

Note:

Table 3-5 Clock Operation (continued) 100 and 120 MHz Values

No.

Characteristics

Symbol

100 MHz

120 MHz

Min

Max

Min

Max

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