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DSP56362P Scheda tecnica(PDF) 70 Page - Freescale Semiconductor, Inc |
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DSP56362P Scheda tecnica(HTML) 70 Page - Freescale Semiconductor, Inc |
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70 / 152 page  External Memory Expansion Port (Port A) DSP56362 Technical Data, Rev. 4 3-44 Freescale Semiconductor Figure 3-24 Bus Release Timings Case 2 (BRT Bit in OMR Set) Table 3-19 Asynchronous Bus Arbitration timing No. Characteristics Expression 100 MHz Unit Min Max 250 BB assertion window from BG input negation. 2 .5* Tc + 5 — 20 ns 251 Delay from BB assertion to BG assertion 2 * Tc + 5 20 — ns Notes: 1. Bit 13 in the OMR register must be set to enter Asynchronous Arbitration mode 2. At 100 MHz it is recommended to use Asynchronous Arbitration mode. 3. If Asynchronous Arbitration mode is active, none of the timings in Table 3-19 is required. 4. In order to guarantee timings 250, and 251, it is recommended to assert BG inputs to different 56300 devices (on the same bus) in a non overlap manner as shown in Figure 3-25. A0–A17 BB AA0–AA3 CLKOUT BR BG RD, WR 223 218 219 214 212 213 221 224 AA0483 |
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