IA186EM-PQF100I-R datasheet(35/133 Pages) INNOVASIC

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IA186EM/IA188EM

Data Sheet

8/16-BIT Microcontrollers

As of Production Version -03

Master Mode

INT2 and INT3 are designated as interrupt type 0eh and 0fh respectively.

The int2 and int3 pins may be configured as the interrupt acknowledge pins inta0_n and inta1_n

respectively in cascade mode.

The value of these registers is 000Fh at reset.

Reserved

LTM MSK

PR2-PR0

Reserved (bits 15-5) – Set to 0.

LTM (bit 4) – Level-Triggered Mode The int2 or int3 interrupt may be edge or level triggered

depending on the value of this bit. If LTM is 1, int2 or int3 is an active high level-sensitive interrupt.

If LTM is 0, int2 or int3 is a rising edge triggered interrupt. The interrupt int2 or int3 must remain

active (high) until acknowledged.

MSK (bit 3) – Mask. The int2 or int3 signal can cause an interrupt if the MSK bit is 0. The int2 or

int3 signal cannot cause an interrupt if the MSK bit is 1. The Interrupt Mask Register has a duplicate

of this bit.

PR2-PR0 (bit 2-0) – Priority. These bits define the priority of the serial port interrupt int2 or int3 in

relation to other interrupt signals. The interrupt priority is the lowest at 7 at reset. The values of PR2

– PR0 are shown in the above table (Priority Level).

I1CON (03ah) – INT0/INT1 CONtrol Register.

I0CON (038h),

(Master Mode)

IINT0 and INT1 are designated as interrupt type 0ch and 0dh respectively.

The int2 and int3 pins may be configured as the interrupt acknowledge pins inta0 and inta1 respectively,

the interrupt acknowledge signals for int0 and int1 in cascade mode.

The value of these registers is 000Fh at reset.

Reserved

SFNM C LTM MSK

PR2-PR0

Reserved (bits 15-7) – Set to 0.

SPNM (bit 6) – Special Fully Nested Mode. This bit enables fully nested mode for int0 or int1 when

set to 1.

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