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IA186EM-PQF100I-R Scheda tecnica(PDF) 48 Page - InnovASIC, Inc |
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IA186EM-PQF100I-R Scheda tecnica(HTML) 48 Page - InnovASIC, Inc |
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48 / 133 page  IA186EM/IA188EM Data Sheet 8/16-BIT Microcontrollers As of Production Version -03 (PB = 1). This bit is reset to 0 when the SDEN output is not active (DE1-DE0 in the SSC register are 00h). DR/DT (bit 1) – Data Receive/Transmit Complete. This bit is set to a 1 when the transmission of data bit 7 is completed (SCLK rising edge) during a transmit or receive operation. This bit is reset by a read of the SSR register, when either the SSD0 or SSD1 register is written, when the SSS register is read (unless the SSI completes an operation and sets the bit in the same cycle), or when both SDEN0 and SDEN1 become inactive. PB (bit 0) SSI Port busy. This bit indicates that a data transmit or receive is occurring when it is set to 1. When set to 0 it indicates that the port is ready to transmit or receive data. 3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com |
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