IA186EM-PQF100I-R datasheet(41/133 Pages) INNOVASIC

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IA186EM/IA188EM

Data Sheet

8/16-BIT Microcontrollers

As of Production Version -03

WD (bit 9) – Watchdog Timer Interrupt In-Service Request. This bit is the In-Service state of the

Watchdog Timer.

I [4:0] (bits 8 - 4) Interrupt Requests. Setting any of these bits to 1 indicates that the relevant

interrupt has a pending interrupt.

D1-D0 (bit 3:2) DMA Channel Interrupt In-Service. This bit is the In-Service state of the respective

DMA channel.

Reserved (bit 1)

TMR (bit 0) – Timer Interrupt Request. This is the timer interrupt state and is the logical OR of the

timer interrupt requests. Setting this bit to 1 indicates that the timer control unit has a pending

interrupt.

Slave Mode

This is a read-only register and such a read supplies the status of the interrupt request bits presented to the

interrupt controller.

When an internal interrupt request (D1, D0, TMR2, TMR1, and TMR0) occurs, the respective bit is set to

1. The internally generated interrupt acknowledge resets these bits.

The REQST register contains 0000h on reset.

12 11

Reserved

TMR2 TMR1

Res TMR0

Reserved (bits 15 – 6)

TMR2 (bit 5) Timer2 Interrupt In Service. Timer 2 is being serviced when this bit is set to 1.

TMR1 (bit 4) Timer1 Interrupt IN Service. Timer 1 is being serviced when this bit is set to 1.

D1-D0 (bit 3:2) DMA Channel Interrupt In Service. The respective DMA channel is being serviced

when this bit is set to 1.

Reserved (bit 1)

TMR0 (bit 0) – Timer Interrupt In Service. Timer 0 is being serviced when this bit is set to 1.

PRIMSK (02ah) – PRIority MaSK Register.

Master and Slave Mode

This register contains a value that sets the minimum priority level at which an interrupt can be generated

by a maskable interrupt.

The PRIMSK register contains 0007h on reset

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IA186EM-PQF100I-R Scheda tecnica(PDF) 41 Page - InnovASIC, Inc