ADIN1100CCPZ-R7 datasheet(65/80 Pages) AD

65 / 80 page

Data Sheet

ADIN1100

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Rev. B | 65 of 80

Table 101. Bit Descriptions for CRSM_MAC_IF_CFG (Continued)

Bits

Bit Name

Description

Reset

Access

[13:9]

RESERVED

Reserved.

0x0

CRSM_RMII_MEDIA_CNV_EN

Media Converter Enable. When this bit is 1, the media converter functionality for the

RMII MAC interface mode is enabled. Note that the media converter functionality can

only be enabled if an RMII MAC interface is being used.

Pin dependent

R/W

[7:5]

RESERVED

Reserved.

0x0

CRSM_RMII_EN

RMII MAC Interface Enable. Enable RMII MAC interface mode. Do not set

CRSM_RGMII_EN and CRSM_RMII_EN at the same time. Configure the MAC

interface only by pins. Do not change by software.

Pin dependent

R/W

[3:1]

RESERVED

Reserved.

0x0

CRSM_RGMII_EN

RGMII MAC Interface Enable. Enable RGMII MAC interface mode. Do not set

CRSM_RGMII_EN and CRSM_RMII_EN at the same time. Configure the MAC

interface only by pins. Do not change by software.

Pin dependent

R/W

CRSM Diagnostics Clock Control Register

Device Address: 0x1E; Register Address: 0x882C, Reset: 0x0002, Name: CRSM_DIAG_CLK_CTRL

CRSM diagnostics clock control.

Table 102. Bit Descriptions for CRSM_DIAG_CLK_CTRL

Bits

Bit Name

Description

Reset

Access

[15:1]

RESERVED

Reserved.

0x1

CRSM_DIAG_CLK_EN

Enable the Diagnostics Clock.

0x0

R/W

Package Configuration Values Register

Device Address: 0x1E; Register Address: 0x8C22, Reset: 0x0002, Name: MGMT_PRT_PKG

The MGMT_PRT_PKG_VAL address allows reading of the package configuration values.

Table 103. Bit Descriptions for MGMT_PRT_PKG

Bits

Bit Name

Description

Reset

Access

[15:6]

RESERVED

Reserved.

0x0

[5:0]

MGMT_PRT_PKG_VAL

Package Type. 2 = ADIN1100 40-lead LFCSP.

0x2

MDIO Control Register

Device Address: 0x1E; Register Address: 0x8C30, Reset: 0x0000, Name: MGMT_MDIO_CNTRL

Table 104. Bit Descriptions for MGMT_MDIO_CNTRL

Bits

Bit Name

Description

Reset

Access

[15:1]

RESERVED

Reserved.

0x0

MGMT_GRP_MDIO_EN

Enable MDIO PHY/Port Group Address Mode. In this mode, the PHY responds to any write or

address operation to the 5-bit PHY/Port Address 31 (decimal) regardless of its own PHY/port address.

This feature is only intended for initialization sequences in multiport applications, must only be set in

those cases, and cleared immediately after the initialization is complete.

0x0

R/W

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