KSZ8565R datasheet(59/235 Pages) MICROCHIP

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DS00002327F-page 59

KSZ8565R

4.11.3

MII MANAGEMENT (MIIM) INTERFACE

The device supports the IEEE 802.3 MII management interface, also known as the management data input/output

(MDIO) interface. This interface allows upper-layer devices to monitor and control the states of the KSZ8565R PHY

blocks, but it does not provide access to the switch registers. An external device with MDC/MDIO capability can read

the PHY status or configure the PHY settings. Details on the MIIM interface can be found in Clauses 22 and 45 of the

IEEE 802.3 Specification.

Use of MIIM conflicts with use of the In-Band Management interface. These interfaces cannot be used simultaneously.

The MIIM interface consists of the following:

• A physical connection that uses a data signal (MDIO) and a clock signal (MDC) for communication between an

external controller and the KSZ8565R. Note that the MDIO signal is open-drain.

• A specific protocol that operates across the two signal physical connection that allows an external controller to

communicate with the internal PHY devices.

• Access to a set of standard, vendor-specific and extended (MMD) 16-bit registers. These registers are also

directly accessible via the SPI and I2C interface options.

The MIIM Interface can operate up to a maximum clock speed of 5MHz. Access is limited to only the registers in the

PHY blocks of ports 1 through 4. Table 4-27 summarizes the MII management interface frame format.

The MIIM PHY address to PHY port mapping is as follows:

• PHY Address 1h to PHY port 1

• PHY Address 2h to PHY port 2

• PHY Address 3h to PHY port 3

• PHY Address 4h to PHY port 4

The MIIM register address space consists of two distinct areas.

• Standard MIIM Registers (Direct)

• MDIO Manageable Device (MMD) Registers (Indirect)

4.11.3.1

Standard MIIM Registers (Direct)

Standard registers provide direct read/write access to a 32-register address space, as defined in Clause 22 of the IEEE

802.3 Specification. Within this address space, the first 16 registers (Registers 0h to Fh) are defined according to the

IEEE specification, while the remaining 16 registers (Registers 10h to 1Fh) are defined specific to the PHY vendor.

The KSZ8565R supports the standard registers listed in Table 4-28 for each PHY port. Each 16-bit MIIM Standard Reg-

ister Address maps to two corresponding 8-bit Port N Register Addresses. The register bit map and description are

located at the 8-bit Port N Register Addresses.

TABLE 4-27:

MII MANAGEMENT INTERFACE FRAME FORMAT

Operation

Mode

Preamble

(32-bit)

Start of

Frame

(2-bit)

Operation

Code

(2-bit)

PHY

Address

(5-bit)

Address

(5-bit)

Turn

Around

(2-bit)

Data

(16-bit)

Idle

Read

All 1s

A[4:0]

Reg[4:0]

D[15:0]

Write

All 1s

A[4:0]

Reg[4:0]

D[15:0]

TABLE 4-28:

STANDARD MIIM REGISTERS

MIIM Standard

(hex)

Port N

(hex)

Description

IEEE-Defined Registers

0xN100 - 0xN101

PHY Basic Control Register

0xN102 - 0xN103

PHY Basic Status Register

0xN104 - 0xN105

PHY ID High Register

0xN106 - 0xN107

PHY ID Low Register

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