KSZ8565R datasheet(8/235 Pages) MICROCHIP

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KSZ8565R

DS00002327F-page 8

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2.0

INTRODUCTION

2.1

General Description

The KSZ8565R is a highly-integrated, IEEE 802.3 compliant networking device that incorporates a layer-2 managed

high-performance Ethernet switch, four 10BASE-T/Te/100BASE-TX physical layer transceivers (PHYs) and associated

MAC units, and one MAC port with a configurable RGMII/MII/RMII interface for direct connection to a host processor/

controller, another Ethernet switch, or an Ethernet PHY transceiver.

The KSZ8565R is built upon industry-leading Ethernet technology, with features designed to offload host processing

and streamline the overall design:

• Non-blocking wire-speed Ethernet switch fabric supports 1 Gbps on RGMII

• Full-featured forwarding and filtering control, including port-based Access Control List (ACL) filtering

• Full VLAN and QoS support

• Traffic prioritization with per-port ingress/egress queues and by traffic classification

• Spanning Tree support

• IEEE 802.1X access control support

The KSZ8565R incorporates full hardware support for the IEEE 1588v2 Precision Time Protocol (PTP), including hard-

ware time-stamping at all PHY-MAC interfaces, and a high-resolution hardware “PTP clock”. IEEE 1588 provides sub-

microsecond synchronization for a range of industrial Ethernet applications.

The KSZ8565R fully supports the IEEE family of Audio Video Bridging (AVB) standards, which provides high Quality of

Service (QoS) for latency sensitive traffic streams over Ethernet. Time-stamping and time-keeping features support

IEEE 802.1AS time synchronization. All ports feature credit based traffic shapers for IEEE 802.1Qav.

The 100Mbps PHYs feature Quiet-WIRE internal filtering to reduce line emissions and enhance immunity to environ-

mental noise. It is ideal for automotive or industrial applications where stringent radiated emission limits must be met.

A host processor can access all KSZ8565R registers for control over all PHY, MAC, and switch functions. Full register

access is available via the integrated SPI or I2C interfaces, and by in-band management via any one of the data ports.

PHY register access is provided by a MIIM interface. Flexible digital I/O voltage allows the MAC port to interface directly

with a 1.8/2.5/3.3V host processor/controller/FPGA.

Additionally, a robust assortment of power-management features including IEEE 802.3az Energy-Efficient Ethernet

(EEE) for power savings with idle link, and Wake-on-LAN (WoL) for low power standby operation, have been designed

to satisfy energy-efficient system requirements.

The KSZ8565R is available in an extended automotive (-40°C to +105°C) temperature range. An internal block diagram

of the KSZ8565R is shown in Figure 2-1.

FIGURE 2-1:

INTERNAL BLOCK DIAGRAM

KSZ8565R

Port 1

10/100

PHY 1

10/100

PHY 2

10/100

PHY 3

10/100

PHY 4

Port 2

Port 3

Port 4

MAC 1

MAC 2

MAC 3

MAC 4

Control

Registers

MAC 5

RGMII/MII/RMII

Address

Lookup

MIB

Counters

Frame

Buffers

Queue

Mgmt.

SPI/I

2C/MIIM

IEEE 1588 /

802.1AS Clock

GPIO

Precision

GPIO

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