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MB90F482 Scheda tecnica(PDF) 38 Page - fujitsu semiconductor |
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MB90F482 Scheda tecnica(HTML) 38 Page - fujitsu semiconductor |
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38 / 120 page ![]() MB90480/485 Series 38 (2) Block Diagram MD1 MD0 CS2 CS1 CS0 SCKE SOE PEN P SBL CL A/D REC RXE TXE PE ORE FRE RDRF TDRE BDS RIE TIE F2MC-16LX BUS SIDR SODR SOT0 SCK0 SIN0 Control signal PPG1 (internal connection) External clock Clock select circuit Receiving status decision circuit µDMAC receiving error generation circuit (to CPU) Receiving clock Receiving control circuit Start bit detect circuit Receive bit counter Receiving parity counter Receiving shifter Receiving control circuit Sending clock Receiving interrupt (to CPU) Sending interrupt (to CPU) Sending control circuit Send start circuit Send bit counter Send parity counter Sending shifter Sending start SMR Control signal SCR SSR Proprietary baud rate generator |
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