MB90F482 datasheet(8/120 Pages) FUJITSU

8 / 120 page

MB90480/485 Series

■ PIN DESCRIPTIONS

(Continued)

Pin No.

Pin name

I/O

circuit

type*3

Function

QFP*1

LQFP*2

Clock (oscillator) input pin

Clock (oscillator) output pin

X0A

Clock (32 kHz oscillator) input pin

X1A

Clock (32 kHz oscillator) output pin

RST

Reset input pin

85 to 92 83 to 90

P00 to P07

(CMOS)

This is a general purpose I/O port. A setting in the port 0 input

resistance register (RDR0) can be used to apply pull-up resistance

(RD00-RD07

= “1”) . (Disabled when pin is set for output.)

AD00 to

AD07

In multiplex mode, these pins function as the external address/data

bus low I/O pins.

D00 to D07

In non-multiplex mode, these pins function as the external data bus

low output pins.

93 to

100

91 to 98

P10 to P17

(CMOS)

This is a general purpose I/O port. A setting in the port 1 input

resistance register (RDR1) can be used to apply pull-up resistance

(RD10-RD17

= “1”) . (Disabled when pin is set for output.)

AD08 to

AD15

In multiplex mode, these pins function as the external address/data

bus high I/O pins.

D08 to D15

In non-multiplex mode, these pins function as the external data bus

high output pins.

1 to 4

99,100,

1, 2

P20 to P23

(CMOS/H)

This is a general purpose I/O port. When the bits of external address

output control register (HACR) are set to "1" in external bus mode,

these pins function as general purpose I/O ports.

A16 to A19

When the bits of external address output control register (HACR) are

set to "0" in multiplex mode, these pins function as address high

output pins (A16-A19).

When the bits of external address output control register (HACR) are

set to "0" in non-multiplex mode, these pins function as address high

output pins (A16-A19).

5 to 8

3 to 6

P24 to P27

(CMOS/H)

This is a general purpose I/O port. When the bits of external address

output control register (HACR) are set to "1" in external bus mode,

these pins function as general purpose I/O ports.

A20 to A23

When the bits of external address output control register (HACR) are

set to "0" in multiplex mode, these pins function as address high

output pins (A20-A23).

When the bits of external address output control register (HACR) are

set to "0" in non-multiplex mode, these pins function as address high

output pins (A20-A23).

PPG0 to

PPG3

Output pins for PPG.

P30

(CMOS/H)

This is a general purpose I/O port.

A00

In non-multiplex mode, this pin functions as an external address pin.

AIN0

8/16-bit up/down timer input pin (ch.0) .

MB90F482 Scheda tecnica(PDF) 8 Page - fujitsu semiconductor

MB90F482 Scheda tecnica(HTML) 8 Page - fujitsu semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL