ELANSC310 datasheet(35/119 Pages) AMD

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Élan™SC310 Microcontroller Data Sheet

PREL IMINARY

are asserted Low immediately after reset, and the

PMC3 signal is asserted High immediately after reset.

Each of the PMC pins can then be programmed to be

High or Low for each of the ÉlanSC310 microcontroller

power management modes.

SUS/RES

Suspend/Resume Operation (Input; Rising Edge)

When the ÉlanSC310 microcontroller is in High Speed

PLL, Low Speed PLL, or Doze mode, a positive edge

on this pin causes the internal logic to step down

through the Power Management modes (one per re-

fresh cycle) until Sleep mode is entered. If in Sleep,

Suspend, or Off mode, a positive edge on this pin

causes the ÉlanSC310 microcontroller to enter the

High Speed PLL mode.

MISCELLANEOUS INTERFACE

LF1, LF2, LF3, LF4 (Analog inputs)

Loop Filters

These pins are used to connect external components

that make up the loop filters for the internal PLLs. For

more information, see “Loop Filters” on page 86.

X1OUT [BAUD-OUT]

14-MHz/UART Output

This can be programmed to be either the 14.336-MHz

clock or the serial baud rate clock for serial infrared de-

vices. The 14.336-MHz output can be used by external

video controllers. As BAUD_OUT, it is 16 x the bit data

rate of the serial port and is used by serial infrared

devices.

X14OUT

14-MHz Output

The Parallel Port AFDT output can be programmed to

become X14OUT, a 14.336-MHz clock.

X32IN, X32OUT

32.768-kHz Crystal Interface

These pins are used for the 32.768-kHz crystal. This is

the main clock source for the ÉlanSC310 microcontrol-

ler and is used to drive the internal Phase-Locked

Loops that generate all other clock frequencies needed

in the system. For more information, see “Crystal Spec-

ifications” on page 84.

LOCAL BUS INTERFACE

The following list of pins is specific to local bus function-

ality. In Local Bus mode, additional ISA pins are also

available. These pins are described in the next section

“Maximum ISA Bus Interface” because these pins are

available in both Local Bus and Maximum ISA Bus

modes.

For more information, see “Maximum ISA Interface ver-

sus Local Bus Interface” on page 60, and Tables 33

and 34 on page 63.

ADS

Local Bus Address Strobe (Output; Active Low)

Local Bus Address Strobe is an active Low address

strobe signal for 386 local bus devices.

BHE

Local Bus Byte High Enable (Output; Active Low)

This signal indicates to the local bus devices that data

is being transferred on the high byte of the data bus.

BLE

Local Bus Byte Low Enable (Output; Active Low)

This signal indicates to the local bus devices that data

is being transferred on the low byte of the data bus.

CPUCLK (PULLUP)

CPU 2X Clock (Output)

This is the timing reference for the local bus device.

The high-speed PLL can be programmed to provide

one of the clock frequencies shown on page 44.

CPURDY

386 CPU Ready Signal (Output; Active Low)

This signal shows the current state of the 386 core

CPU’s CPURDY signal.

CPURST (RSVD)

CPU Reset (Output; Active High)

This signal is used to force the local bus device to an

initial condition. It is also used to allow the local bus de-

vice to synchronize to the CPUCLK. This signal is

taken directly from the internal CPU reset.

D/C

Local Bus Data/Control (Output; Active Low)

This signal indicates to the local bus devices that the

current cycle is either a Data cycle or a Control cycle.

A Low on this signal indicates that the current cycle is

a Control cycle.

LDEV (RSVD)

Local Bus Device Select (Input; Active Low)

This signal is used by the local bus devices to signal

that they will respond to the current cycle. If LDEV is

not driven active by the time required in Table 51 on

page 98, then the cycle defaults to an ISA bus cycle.

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