ELANSC310 datasheet(52/119 Pages) AMD

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Élan™SC310 Microcontroller Data Sheet

PREL IMINARY

data onto the parallel port data bus, as shown in

Figure 5.

When the ÉlanSC310 microcontroller parallel port is

configured for Bidirectional mode operation, the

PPDWE pin is reconfigured via firmware to function as

the Parallel Port Data Register address decode

(PPDCS). The PPOEN output from the ÉlanSC310 mi-

crocontroller is controlled via the Parallel Port Control

output enable of the external parallel port data latch. By

setting this bit, the parallel port data latch is disabled,

and then data can be transferred from an external par-

allel port device into the ÉlanSC310 microcontroller

through an external 244 type buffer. A typical bidirec-

tional Parallel Port Data Bus implementation is shown

in Figure 6 on page 53.

If the VCC5 supply pins are connected to a 5-V power

supply, then the Parallel Port control signals will be

driven by 5-V outputs and can be connected directly to

the parallel port connector. If VCC5 is connected to

3.3 V, the parallel port control signals should be trans-

lated to 5 V.

The ÉlanSC310 CPU also supports Enhanced Parallel

Port (EPP) mode. The EPP mode pins are defined in

Table 24.

In Normal mode, the outputs shown in Table 24 func-

tion as open-collector or open-drain outputs. In EPP

mode, these outputs must function as standard CMOS

outputs that are driven High and Low. Figure 6 shows

the design that should be used to support EPP mode.

Figure 5.

ÉlanSC310 Microcontroller

Unidirectional Parallel Port Data Bus

Implementation

374 Octal D Flip Flop

SD7–SD0

PPDWE

Parallel Port

Data Bus

CLK

Table 24.

Parallel Port EPP Mode Pin Definition

Normal

Mode

EPP

Mode

Description

STRB

WRITE

EPP write signal. This signal is

driven active during writes to

the EPP data or address regis-

ter.

AFDT

DSTRB

EPP data strobe. This signal is

driven active during reads or

writes to the EPP data register.

SLCTIN

ASTRB

EPP address strobe. This sig-

nal is driven active during

reads or writes to the EPP ad-

dress register.

ACK

INTR

EPP interrupt. This signal is an

input used by the EPP device

to request service.

BUSY

WAIT

EPP wait. This signal is used to

add wait states to the current

cycle. It is similar to the ISA IO-

CHRDY signal.

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