ELANSC310 datasheet(44/119 Pages) AMD

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Élan™SC310 Microcontroller Data Sheet

PREL IMINARY

In the PLL Block Diagram, the INT_PLL is the Interme-

diate PLL, and is used to multiply the 32.768-kHz input

frequency by 45 to produce a 1.4746-MHz input for use

by the LS_PLL and the VID_PLL. The LS_PLL, or Low-

Speed PLL, is used to again multiply the 1.4746-MHz

input by 25 to produce a 36.864-MHz output. This out-

put of the LS_PLL is then divided down to provide the

frequencies shown in Table 20.

The LS_PLL also generates a 2.048-MHz signal used

by the VID_PLL or Video PLL to generate the 14.336-

MHz clock. This frequency is also available on the

X1OUT pin for use by an external video controller if se-

lected. This frequency should only be used to drive an

LCD panel.

The HS_PLL can be programmed to provide one of the

high-speed CPU clock frequencies shown in Table 19.

ÉlanSC310 Microcontroller

Power Management

Dynamic CPU clock switching is the primary form of

power management in the ÉlanSC310 microcontroller.

When the system is in the High-Speed PLL mode, the

ÉlanSC310 microcontroller can be configured to use

the High-Speed clock output of the PLL for main mem-

ory, local bus accesses, CPU idle cycles, and ROM

accesses configured to use the High-Speed clock. Dur-

ing cycles to I/O devices, ROM and other external ISA

devices, the CPU clock is dynamically switched to the

output of the Low-Speed PLL.

During operation in Low-Speed PLL mode, the CPU

clock is driven from Low-Speed clock output of the

Low-Speed PLL divide chain. The CPU clock fre-

quency used during Low Speed mode is programma-

ble to the following frequencies: 4.608 MHz, 2.304

MHz, 1.152 MHz, and 0.567 MHz. During Doze, Sleep,

and Suspend modes of operation, the CPU clock is

normally stopped. This clock operates at 9.216 MHz

when it is running.

Slow-refresh and self-refresh DRAMs are supported by

the ÉlanSC310 microcontroller. The refresh timer

source and the refresh rate are selectable. When the

CPU clock is stopped, the only clock source for refresh

is the 32-kHz clock. CAS-before-RAS DRAM refresh is

performed.

When the DMA subsystem is idle, the DMA clock con-

trol logic stops the clock input to the DMA controllers.

The DMA clock is started whenever any of the DREQ

inputs go High. When the DMA cycle is in progress, the

DMA clock remains active as long as a DREQ input is

High or the internal AEN signal is active.

To reduce power consumption in Doze, Sleep, and

Suspend modes, the CPU clock is turned off. To further

reduce the power consumption in these three modes,

the High-Speed PLL is shut off. The Low-Speed PLL is

left on by default, but can be programmed to turn off in

all three modes.

For information about the signals associated with

power management (ACIN, BL4–BL1, EXTSMI, LPH,

PGP3–PGP0, PMC4–PMC0, and SUS/RES), see

“Power Management Interface” on page 34. For more

information, see Chapter 1 of the

ÉlanTMSC310 Micro-

controller Programmer’s Reference Manual, order

#20665.

Table 19.

High-Speed CPU Clock Frequencies

2 x CPU Frequency

HS_PLL Output Frequency

40 MHz

39.496 MHz

50 MHz

50.023 MHz

66 MHz

65.829 MHz

Table 20.

PLL Output

Phase-Locked Loops

Frequency

Where Used

INT_PLL

1.4746 MHz

LS_PLL and VID_PLL

LS_PLL

36.864 MHz

Divide by 2

1.8432 MHz

16450 UART clock

1.1892 MHz

8254 Timer clock

HS_PLL

39.496 MHz, 50.023 MHz,

or 65.829 MHz

Input to high speed/low speed MUX

VID_PLL

14.336 MHz

External video controller, if using an LCD panel

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