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ELANSC310 Scheda tecnica(PDF) 102 Page - Advanced Micro Devices |
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ELANSC310 Scheda tecnica(HTML) 102 Page - Advanced Micro Devices |
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102 / 119 page ![]() 102 Élan™SC310 Microcontroller Data Sheet PREL IMINARY Notes: 1. This is the timing when DOSCS is qualified with MEMR or MEMW, (Bit 4 of ROM Configuration 3 Register, Index B8h, = 0). 2. This is the timing when DOSCS is configured as an address decode, (Bit 4 of ROM Configuration 3 Register, Index B8h, = 1). These timings are based on default wait state settings, set for 5 wait states with bit 2 in Index 50h and Bits 0 and 1 in Index 62h equal to 0, and required initial programming. These timings may be modified via the MMS Memory Wait State 1 Register, Index 62h, the Command Delay Register, Index 60h, and the MMS Memory Wait State 2 Register, Index 50h. (See the ÉlanTMSC310 Microcontroller Programmer’s Reference Manual , order #20665.) Table 53. DOS ROM Read/Write 8 Bit Cycle (See Figure 42) Symbol Parameter Description Notes Preliminary Units Min Max t1a SA stable to DOSCS active 1 160 ns t1b SA stable to DOSCS active 2 5 ns t2a SA hold from DOSCS inactive (write) 1 50 ns t2b SA hold from DOSCS inactive (read) 1 0 ns t3a DOSCS pulse width (read) 1 550 ns t3b DOSCS pulse width (write) 1 500 ns t4a MEMW active to DOSCS active 1 4 ns t4b MEMR active to DOSCS active 1 4 ns t5a DOSCS hold from MEMW inactive 1 0 ns t5b DOSCS hold from MEMR inactive 1 0 ns t6 RDDATA setup to command inactive 40 ns t7 RDDATA hold from command inactive 0 ns t8 WRDATA setup to command inactive 90 ns t9 WRDATA hold from command inactive 50 ns t10 DBUFOE active from command 5 ns t11a DBUFOE hold from MEMW 50 ns t11b DBUFOE hold from MEMR –2 ns t12 ENDIRH, ENDIRL setup to MEMR 50 ns t13 ENDIRH, ENDIRL hold from MEMR –3 ns t14 DOSCS active to command active 2 170 ns t15 DOSCS hold from SA 2 5 ns |
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