ADL5309ACBZ-R7 datasheet(16/25 Pages) AD

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Data Sheet

ADL5309

THEORY OF OPERATION

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Rev. A | 16 of 25

given in Equation 11. Note that setting either PDBG_FIX = 1 or

PDBG = 0 disables the RT.

RT=15.625× 1−PDBG_FIX ×PDBG (11)

The RT becomes effective with values greater than the ITH, and the

ITH is controlled by PDBG in SREG_07 and IDZ in SREG_08. It can

be expressed as the following equation:

ITH=32 μA× 100×IDZ−PDBG

PDBG× 1−PDBG_FIX

(12)

Because the minimum functional value for IDZ is 1, the smallest

value for ITH is obtained for IDZ = 1 and PDBG = 63, resulting in

ITH = 18 μA. When PDBG_FIX = 1, ITH becomes infinite, effectively

disabling RT. If IDZ is set to zero, the offset calibration is lost.

The initial bias voltage (or offset voltage) between the PDB pin and

the INP pin, can be adjusted using Register SREG_08, Register

SREG_0A, and Register SREG_0B. Additionally, the initial bias

voltage is dependent on PDBG and PDBG_FIX. The bit field IPDB

in Register SREG_08 provides a coarse adjustment in 25 mV steps

that is the same for both channels. The contribution of PDBG in

SREG_07 is dependent on the state of the PDBG_FIX flag. For

input currents less than the ITH, the offset voltage in mV is given by

the following equation:

VOS=62.5×PDBG×PDBG_FIX+25

×IPDB+0.15× OS−128

(13)

Note that |V_PDB1 − V_INP1| and |V_PDB2 − V_INP2| are

minimized in the factory at low input currents for IPDB = 0 and

PDBG_FIX = 0 by trimming OS1 and OS2 and therefore V_OS is

not necessarily 0 mV for OS1 = OS2 = 128. Further insight into this

relationship between bandwidth and input current can be obtained

from Figure 21.

BANDWIDTH

The bandwidth of logarithmic TIAs changes with the IPD, resulting in

low bandwidth at low input currents that gradually increases to high-

er bandwidths at higher current levels. In general, bandwidth and

gain have an inverse relationship to each other, so increasing the

gain of an amplifier typically reduces its bandwidth and vice versa.

Logarithmic TIAs are no exception to this rule. Using Equation 1,

the small-signal gain (RT) of a TIA, (that is, the change in output

voltage due to a (small) change in IPD) can be expressed as the

following equation:

Zt=dVOUTdIPD= SLOPE

ln10 ×IPD

(14)

where: Zt is the small signal gain.

Due to the inherent dynamic range compression by the logarithm,

the TIA gain at low input levels is very high, so low bandwidth is to

be expected. Similarly, the RT at high input currents is much lower

and expected to result in higher bandwidth. Further insight into this

relationship between bandwidth and input current can be obtained

from Figure 1, depicting a simplified schematic of a logarithmic TIA.

Usually, the overall topology is a negative feedback amplifier using

a diode or the base-emitter junction of a bipolar transistor to estab-

lish the logarithmic transfer from IIN to VOUT. Without feedback,

that is if the gain of the operational amplifier (op amp) were zero,

the impedance (to ground) at the input node would be high. Most

of the current from the source should flow into the diode, so a

small parasitic capacitance of the photodiode or circuit board has

a major impact on the (open-loop) bandwidth of the circuit. The

loop gain in the amplifier reduces the impedance at the input

node by a factor approximately equal to the loop gain, which is

roughly the product of the op amp gain, input impedance, and the

feedback diode transconductance. If the loop gain were infinite,

the closed-loop input impedance of the TIA would become zero,

that is, a virtual ground, and the current through the feedback

diode would be precisely equal to the source current (IS). In a

practical amplifier where the op amp has high but finite gain, an

increase of the RT gain (ZT) corresponds to a decrease of the diode

transconductance (which ideally equals the inverse of ZT), and thus,

the amplifier loop gain decreases. In turn, a decrease of the loop

gain increases the closed-loop input impedance of the amplifier and

(given that the input capacitance is roughly fixed) decreases the

amplifier bandwidth. In order to maintain a bandwidth that is as

wide as possible, it is critical to minimize capacitive loading of the

TIA input pins.

NOISE

The noise level produced by a logarithmic TIA is also dependent

on the IINP. The VOUT noise is highest at low input currents (cor-

responding to the highest small-signal gain), and lowest at high

input current levels. Figure 24 and Figure 26 show the spot noise

spectral density vs. IINP graph for CF = 0 and CF = 15. For low input

currents, one of the most dominant noise sources is the 1/f noise

of the input negative channel metal-oxide semiconducter (NMOS).

shown in Figure 43, which produces a 1/f noise voltage at the input

node.

With a capacitive load at the input, this noise voltage causes an

input 1/f noise current and can produce a hill-shaped spot noise

spectral density curve. Therefore, it is important to minimize the

source capacitance by choosing a photodiode with the lowest

possible equivalent parallel capacitance and shortest possible trace

to the input node. A trade-off between noise density and bandwidth

at low IINP can be made by setting register CF (as shown in Figure

23 and Figure 18) with the minimum bandwidth and lowest noise

density for CF = 15 (default) and the maximum bandwidth and

highest noise density for CF = 0.

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