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TMS320DM6446 Scheda tecnica(PDF) 81 Page - Texas Instruments |
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TMS320DM6446 Scheda tecnica(HTML) 81 Page - Texas Instruments |
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81 / 231 page  www.ti.com 3.6 Emulation Control TMS320DM6446 Digital Media System-on-Chip SPRS283E – DECEMBER 2005 – REVISED MARCH 2007 Table 3-33. HPI and EMIFA/ATA Pin Multiplexing PINMUX0 REGISTER MULTIPLEXED PINS BIT FIELDS HR/W/ HRDY/ HDS1/ HDS2/ HCNTLB/ HINT/ HD[15:0]/ HPI ATA HCS/ HHWIL/ HCNTLA/ INTRQ/ RDY/BSY/ DIOR/ DIOW/ ATA2/ ATA0/ DD[15:0]/ EN EN EM_CS2 EM_A[1] EM_A[2] EM_R/W EM_WAIT EM_OE EM_WE EM_A[0] EM_BA[0] EM_D[15:0] 0 0 EM_CS2 EM_A[1](1) EM_R/W RDY/BSY EM_OE EM_WE EM_A[2](1) EM_A[0](1) EM_BA[0] EM_D[15:0] 0 1 EM_CS2 EM_A[1](1) INTRQ EM_WAIT DIOR DIOW EM_A[2](1) EM_A[0](1) ATA0 DD[15:0] 1 - HCS HHWIL HR/W HRDY HDS1 HDS2 HCNTLA HCNTLB HINT HD[15:0] (1) This pin shares GPIO functionality and is set by AEAW[4:0] as shown in Table 3-12, Table 3-13, and Table 3-14. The flexibility of the DM644x architecture allows either the ARM or DSP to control the various peripherals (setup registers, service interrupts, etc.). While this assignment is purely a matter of software convention, during an emulation halt it is necessary for the device to know which peripherals are associated with the halting processor so that only those modules receive the suspend signal. This allows peripherals associated with the other (unhalted) processor to continue normal operation. The SUSPSRC register indicates the emulation suspend source for those peripherals which support emulation suspend. The SUSPSRC register format is shown in Figure 3-9. Brief details on the peripherals which correspond to the register bits is given in Table 3-34. When the associated SUSPSRC bit is ‘0’, the peripheral’s emulation suspend signal is controlled by the ARM emulator and when set to ‘1’ it is controlled by the DSP emulator. Figure 3-9. Emulation Suspend Source Register (SUSPSRC) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 VICP VICP TIMR2 TIMR1 TIMR0 GPIO PWM2 PWM1 PWM0 SPI UART2 UART1 UART0 I2C ASP Rsvd SRC EN SRC SRC SRC SRC SRC SRC SRC SRC SRC SRC SRC SRC SRC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HPI USB EMAC Rsvd Rsvd Rsvd Reserved SRC SRC SRC R-000 R/W-0 R-00 R/W-0 R-000 R/W-0 R-0 0000 LEGEND: R = Read, W = Write, n = value at reset Table 3-34. SUSPSRC Register Description Name Description VICPSRC Video Imaging Coprocessor emulation suspend source 0 = ARM emulation suspend 1 = DSP emulation suspend VICPEN Video Imaging Coprocessor emulation suspend enable 0 = Emulation suspend ignored by VICP 1 = VICP emulation suspend enabled TIMR2SRC Timer2 (WD Timer) emulation suspend source 0 = ARM emulation suspend 1 = DSP emulation suspend TIMR1SRC Timer1 emulation suspend source 0 = ARM emulation suspend 1 = DSP emulation suspend TIMR0SRC Timer0 emulation suspend source 0 = ARM emulation suspend 1 = DSP emulation suspend Submit Documentation Feedback Device Configurations 81 |
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