TMS320DM6446 datasheet(2/231 Pages) TI

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1.2 Description

TMS320DM6446

Digital Media System-on-Chip

SPRS283E – DECEMBER 2005 – REVISED MARCH 2007

• External Memory Interfaces (EMIFs)

–

IEEE 802.3 Compliant

–

32-Bit DDR2 SDRAM Memory Controller

–

Media Independent Interface (MII)

With 256M-Byte Address Space (1.8-V I/O)

• VLYNQ™ Interface (FPGA Interface)

–

Asynchronous16-Bit Wide EMIF (EMIFA)

• Host Port Interface (HPI) with 16-Bit

With 128M-Byte Address Reach

Multiplexed Address/Data

• Flash Memory Interfaces

• USB Port With Integrated 2.0 PHY

• NOR (8-/16-Bit-Wide Data)

–

USB 2.0 High-/Full-Speed (480-Mbps) Client

• NAND (8-/16-Bit-Wide Data)

–

USB 2.0 High-/Full-/Low-Speed Host

• Flash Card Interfaces

(Mini-Host, Supporting One External

–

Multimedia Card (MMC)/Secure Digital (SD)

Device)

with Secure Data I/O (SDIO)

• Three Pulse Width Modulator (PWM) Outputs

–

Compact Flash Controller With True IDE

• On-Chip ARM ROM Bootloader (RBL) to Boot

Mode

From NAND Flash or UART

–

SmartMedia

• ATA/ATAPI I/F (ATA/ATAPI-6 Specification)

• Enhanced Direct-Memory-Access (EDMA)

• Individual Power-Saving Modes for ARM/DSP

Controller (64 Independent Channels)

• Flexible PLL Clock Generators

• Two 64-Bit General-Purpose Timers (Each

Configurable as Two 32-Bit Timers)

• IEEE-1149.1 (JTAG) Boundary-

Scan-Compatible

• One 64-Bit Watch Dog Timer

• Up to 71 General-Purpose I/O (GPIO) Pins

• Three UARTs (One with RTS and CTS Flow

(Multiplexed With Other Device Functions)

Control)

• 361-Pin Pb-Free BGA Package

• One Serial Port Interface (SPI) With Two

(ZWT Suffix), 0.8-mm Ball Pitch

Chip-Selects

• 0.09-µm/6-Level Cu Metal Process (CMOS)

• Master/Slave Inter-Integrated Circuit (I2C

Bus™)

• 3.3-V and 1.8-V I/O, 1.2-V Internal

• Audio Serial Port (ASP)

• Applications:

–

I2S

–

Digital Media

–

AC97 Audio Codec Interface

–

Networked Media Encode/Decode

–

Standard Voice Codec Interface (AIC12)

–

Video Imaging

• 10/100 Mb/s Ethernet MAC (EMAC)

The TMS320DM6446 (also referenced as DM6446) leverages TI’s DaVinci™ technology to meet the

networked media encode and decode application processing needs of next-generation embedded devices.

The DM6446 enables OEMs and ODMs to quickly bring to market devices featuring robust operating

systems support, rich user interfaces, high processing performance, and long battery life through the

maximum flexibility of a fully integrated mixed processor solution.

The dual-core architecture of the DM6446 provides benefits of both DSP and Reduced Instruction Set

Computer (RISC) technologies, incorporating a high-performance TMS320C64x+ DSP core and an

ARM926EJ-S core.

The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and

processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and

memory system can operate continuously.

The ARM core incorporates:

• A coprocessor 15 (CP15) and protection module

• Data and program Memory Management Units (MMUs) with table look-aside buffers.

• Separate 16K-byte instruction and 8K-byte data caches. Both are four-way associative with virtual

index virtual tag (VIVT).

Digital Media System-on-Chip (DMSoC)

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