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TMS320DM6446 Scheda tecnica(PDF) 21 Page - Texas Instruments |
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TMS320DM6446 Scheda tecnica(HTML) 21 Page - Texas Instruments |
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21 / 231 page  www.ti.com 2.6 Pin Assignments TMS320DM6446 Digital Media System-on-Chip SPRS283E – DECEMBER 2005 – REVISED MARCH 2007 Table 2-4. Configuration Memory Map Summary (continued) START END SIZE ARM/EDMA C64x+ ADDRESS ADDRESS (Bytes) 0x01C4 2034 0x01C4 23FF 1K - 52 Reserved 0x01C4 2400 0x01C4 7FFF 23K 0x01C4 8000 0x01C4 83FF 1K ARM Interrupt Controller 0x01C4 8400 0x01C5 FFFF 95K Reserved 0x01C6 0000 0x01C6 3FFF 16K Reserved 0x01C6 4000 0x01C6 5FFF 8K USB2.0 Registers / RAM 0x01C6 6000 0x01C6 67FF 2K ATA/CF 0x01C6 6800 0x01C6 6FFF 2K SPI 0x01C6 7000 0x01C6 77FF 2K GPIO 0x01C6 7800 0x01C6 7FFF 2K HPI HPI 0x01C6 8000 0x01C6 FFFF 32K Reserved 0x01C7 0000 0x01C7 3FFF 16K VPSS Registers 0x01C7 4000 0x01C7 FFFF 48K Reserved 0x01C8 0000 0x01C8 0FFF 4K EMAC Control Registers 0x01C8 1000 0x01C8 1FFF 4K EMAC Control Module Registers Reserved 0x01C8 2000 0x01C8 3FFF 8K EMAC Control Module RAM 0x01C8 4000 0x01C8 47FF 2K MDIO Control Registers 0x01C8 4800 0x01C8 4FFF 2K Reserved 0x01C8 5000 0x01CB FFFF 236K 0x01CC 0000 0x01CD FFFF 128K VICP VICP 0x01CE 0000 0x01CF FFFF 128K Reserved 0x01D0 0000 0x01DF FFFF 1M Reserved 0x01E0 0000 0x01E0 0FFF 4K EMIFA Control 0x01E0 1000 0x01E0 1FFF 4K VLYNQ Control Registers 0x01E0 2000 0x01E0 3FFF 8K ASP ASP 0x01E0 4000 0x01E0 FFFF 48K Reserved 0x01E1 0000 0x01E1 FFFF 64K MMC/SD/SDIO Reserved 0x01E2 0000 0x01E3 FFFF 128K Reserved 0x01E4 0000 0x01FF FFFF 1792K 0x0200 0000 0x03FF FFFF 32M EMIFA Data/Code (CS2) EMIFA Data (CS2) 0x0400 0000 0x05FF FFFF 32M EMIFA Data/Code (CS3) EMIFA Data (CS3) 0x0600 0000 0x07FF FFFF 32M EMIFA Data/Code (CS4) EMIFA Data (CS4) 0x0800 0000 0x09FF FFFF 32M EMIFA Data/Code (CS5) EMIFA Data (CS5) 0x0A00 0000 0x0BFF FFFF 32M Reserved Reserved 0x0C00 0000 0x0FFF FFFF 64M VLYNQ (Remote) Extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in the smallest possible package. Pin multiplexing is controlled using a combination of hardware configuration at device reset and software programmable register settings. For more information on pin muxing, see Section 3.5.2, Multiplexed Pin Configurations, of this document. Submit Documentation Feedback Device Overview 21 |
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