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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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STAMP0 Scheda tecnica(PDF) 21 Page - STMicroelectronics |
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STAMP0 Scheda tecnica(HTML) 21 Page - STMicroelectronics |
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21 / 62 page  STAMP0 Architecture DocID028639 Rev 1 21/62 4.3.5 Averaging based RMS calculation Figure 10: "RMS calculation data path" shows the architecture implementing the RMS block. In particular the absolute value of the two’s complement input is taken first to reduce the number of bits involved, and finally the signal is low-pass filtered. Figure 10: RMS calculation data path The low-pass filtering solution is implemented with a first-order infinite impulse response filter (IIR filter). The architecture of this filter is depicted in Figure 11: "IIR filter", the Z- transfer filter function is described in Equation 2 below. Figure 11: IIR filter Equation 2 ������������������������������������������������ = 11−(1−2−������������)������������−1 where 2 –p is the actual operand of the filter In the STAMP0 device the P value can be programmed through the I²C register (Reg. 0x23 bits B7, B6, B5 and B4) and the default value is set to zero. 4.4 Reset There are two types of resets in the STAMP0: • Hard reset: the RESET_N pin is low • Soft reset: the I²C register Reg. 0x00 is written to any value Obsolete Product(s) - Obsolete Product(s) |
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