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STAMP0 Scheda tecnica(PDF) 39 Page - STMicroelectronics |
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STAMP0 Scheda tecnica(HTML) 39 Page - STMicroelectronics |
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39 / 62 page ![]() STAMP0 I²C registers DocID028639 Rev 1 39/62 Bit R/W RST Name Description 6 R/W 0 DATA_ALIGN TDM data alignment 0: non delayed 1: delayed 5 R/W 0 SLOT_SIZE TDM slot size: 0: 16 bits 1: 32 bits 4 R/W 0 SCK_RATE TDM SCK rate: 00: 64 Fs 01: 128 Fs 10: 256 Fs 11: reserved 3 R/W 1 2 R/W 0 DATA_FSY_VALID Data and frame sync valid: 0: DATA and FSY valid on the rising edge of SCK 1: DATA and FSY valid on the falling edge of SCK 1 R/W 0 FRAME_START Frame start: 0: on the rising edge of SCK 1: on the falling edge of SCK 0 R/W 1 TDM_EN TDM interface enable: 0: disabled 1: enabled 5.2.11 Channel 1 and 2 mapping configuration register (reg. 0x0A) B7 B6 B5 B4 B3 B2 B1 B0 SLOT1S SLOT2S 0000 (See Table 12: "TDM slots and channel mapping") 0001 (See Table 12: "TDM slots and channel mapping") Table 12: TDM slots and channel mapping R/W B7/B3 B6/B2 B5/B1 B4/B0 Channel TDM slots R/W 0 0 0 0 CH1 SLOTX R/W 0 0 0 1 CH2 R/W 0 0 1 0 CH3 R/W 0 0 1 1 CH4 R/W 0 1 0 0 CH5 R/W 0 1 0 1 CH6 R/W 0 1 1 0 CH7 R/W 0 1 1 1 CH8 R/W 1 0 0 0 All zeros Obsolete Product(s) - Obsolete Product(s) |
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