STAMP0 datasheet(27/62 Pages) STMICROELECTRONICS

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STAMP0

Architecture

DocID028639 Rev 1

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4.7

Read operation

4.7.1

Current address byte read

Following the START condition, the master sends a device select code with the RW bit set

to 1. The slave acknowledges this and then responds by sending one byte of data. The

master then terminates the transfer by generating a STOP condition.

4.7.2

Current address multi-byte read

The multi-byte read modes can start from any internal address. Sequential data bytes are

read from sequential addresses within the slave. The master acknowledges each data byte

read and then generates a STOP condition, terminating the transfer.

4.7.3

Random address byte read

Following the START condition, the master sends a device select code with the RW bit set

to 0. The slave acknowledges this and then the master writes the internal address byte.

After receiving the internal byte address, the slave again responds with an

acknowledgement. The master then initiates another START condition and sends the

device select code with the RW bit set to 1. The slave acknowledges this and then

responds by sending one byte of data. The master then terminates the transfer by

generating a STOP condition.

4.7.4

Random address multi-byte read

The multi-byte read mode can start from any internal address. Sequential data bytes are

read from sequential addresses within the slave. The master acknowledges each data byte

read and then generates a STOP condition, terminating the transfer.

Figure 19: Write mode sequence

Figure 20: Read mode sequence

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STAMP0 Scheda tecnica(PDF) 27 Page - STMicroelectronics