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DRV8860PWPR Scheda tecnica(PDF) 21 Page - Texas Instruments |
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DRV8860PWPR Scheda tecnica(HTML) 21 Page - Texas Instruments |
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21 / 45 page ![]() Data Register Contents A LATCH CLK 1 2 3 4 5 6 7 8 A_D8 A_D7 A_D6 A_D5 A_D4 A_D3 A_D2 A_D1 1 x x 1 2 1 2 3 3 4 DOUT 1 / DIN 2 Data Register 1 1 2 3 4 xxxxxxxxxx DOUT 2 Data Register Contents B Data Register 2 9 10 11 12 13 14 15 A_D8 A_D7 A_D6 A_D5 A_D4 A_D3 A_D2 xxxxxxxxxx B_D8 B_D7 B_D6 B_D5 B_D4 B_D3 B_D2 B_D1 xxxxxxxxxxxx 16 A_D1 xxx Data Register Contents A LATCH CLK 1 2 3 4 5 6 7 8 xxxxx xxxx A_D8 A_D7 A_D6 A_D5 A_D4 A_D3 A_D2 A_D1 1 xx 1 2 1 2 3 3 4 DOUT Data Register 1 2 3 4 xxxxxxxxxxx DRV8860, DRV8860A www.ti.com SLRS065E – SEPTEMBER 2013 – REVISED NOVEMBER 2015 8.5.1.3.3 Special command: Read Data Register When Read-Data-Register command is issued, internal output data register content will be copied to internal shift register and following CLK will shift this content out from DOUT pin. This provides a mechanism for system to verify the output data is correctly programmed. It makes system more robust in noisy system. Figure 24. Reading Data Register – Single Device Figure 25. Reading Data Register – Daisy Chain Figure 26. Reading Data Register – Data Flow Copyright © 2013–2015, Texas Instruments Incorporated Submit Documentation Feedback 21 Product Folder Links: DRV8860 DRV8860A |
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